低剂量辐照条件下的MOSFET因辐照导致的阈值电压漂移的模拟

推导了MOSFET器件阈值电压漂移与辐照剂量和辐照剂量率之间的解析关系,模型计算结果与实验吻合较好。该模型物理意义明确,参数提取方便,适合于低辐照总剂量条件下的MOS器件与电路的模拟。并进一步讨论了MOSFET的辐照敏感性。结果表明,尽管PMOS较之NMOS因辐照引起的阈值电压漂移的绝对量更大,但从MOSFET阈值电压漂移量的摆幅这一角度来看,在低剂量辐照条件下NMOS较之PMOS显得对辐照更为敏感。这一研究结果可能为辐照剂量学提供新的应用思路。     

聚焦离子束加工微锥形结构的制造误差分析

聚焦离子束(FIB)纳米制造技术已经成为微纳米尺度功能器件加工的一种重要方法,利用聚焦离子束直写加工可实现复杂二维微纳结构的高精度制造.然而由于离子溅射产额随入射角度非线性变化规律、再沉积现象及离子束能量分布特性的综合影响,FIB在三维结构加工中会存在复杂形貌误差.针对FIB加工凹面中存在的典型平底现象这一形貌误差进行了分析和实验研究,通过仿真分析和FIB加工直径4,μm锥形凹坑结构的实验验证,阐明了聚焦离子束高斯能量分布特性与溅射产额规律耦合是产生平底现象的主要原因,为FIB三维结构加工的误差的修正提供了重要的基础和依据.     

硅中硼磷的横向扩散及其引起的CMOS LSI失效问题

实验发现,硼磷通过掩膜窗口向硅中扩散时,横向与纵向扩散深度之比 y_j/x_j 不是一个常数,而是随扩散温度的降低增大。此外,对于硼和磷的扩散来说,这个比值是不同的,且有(y_j/x_j)_B>(y_j/x_j)_P。通过解剖一些实际的 CMOS LSI 芯片结构发现,无论是采用常规工艺,或者是采用全离子注入技术,其失效的一种重要模式是 PMOS FET源、漏区硼扩散横向连通。分析了产生这种失效模式的机理。并提出在设计 CMOS LSI 时,适当调整 NMOS FET 和 PMOS FET 的沟道长度,有利于提高成品率和电路性能。     

基于耦合和负反馈的宽带低噪声放大器架构

为了改善现有宽带低噪声放大器(LNA)拓扑结构电路的性能,文中提出了一个交叉耦合和负反馈技术相结合的宽带低噪声放大器架构.该LNA基于复合NMOS/PMOS交叉耦合的无电感宽带差分并联反馈共源低噪声放大器(SFCS-LNA),进一步在输出端和输入端增加交叉连接的PMOS管,引入新的负反馈结构,通过对所引入PMOS管的跨导进行调节,增加了LNA输入匹配的自由度,以解决原复合NMOS/PMOS交叉耦合SFCS-LNA的反馈电阻受限于输入匹配的问题,从而在保证输入匹配的同时提高反馈电阻的阻值,改善LNA中的噪声、输入匹配和增益之间相互制约的矛盾.结果表明,该LNA架构能有效降低LNA的噪声系数和提高LNA的电压增益.     

基于聚焦离子束铣削技术的微刀具制备

提出了一种利用聚焦离子束(FIB)技术的铣削功能制备微细切削刀具的方法,通过设置恰当的离子束参数及精确控制刀具的不同刀面相对离子束的位置,可以获得具有高精度特征尺寸、锋锐刃口且复杂形状的微刀具.被加工刀具的典型特征尺寸为5～50,μm,可加工各种不同截面形状的微刀具.对硬质合金材料的毛坯进行FIB铣削,获得了宽度为7.65,μm、刃口半径小于30,nm的矩形微刀具.通过在超精密车床上进行加工试验,结果表明,FIB铣削的微刀具具有很好的加工性能.     

基于负微分电阻特性的SET/CMOS反相器

基于单电子晶体管(SET)和PMOS管串联产生的负微分电阻(NDR)特性,提出了一种新型的SET/CMOS反相器.该反相器利用NDR特性与NMOS负载管的电流-电压特性构成两个单稳态点,实现反相功能.应用HSPICE仿真器,采用精准的单电子晶体管的子电路模型及22nm CMOS预测技术模型对该反相器进行仿真,结果表明:该反相器的功能正确,具有比传统CMOS反相器更低的功耗;与其它单电子反相器相比,该反相器可在室温下实现输出电压全摆幅,且具有较低的传输延迟.     

用于MOS功率集成电路的VVMOS和NMOS相容技术研究

本文介绍了VVMOSFET和NMOSFET单片集成时阈值电压容差的理论估算和工艺试验结果,二者符合得较好.结果指出,即使用常规工艺制造技术把VVMOS功率晶体管相容集成到NMOS电路中去亦是可能的.     

碳纳米管场效应晶体管:现状和未来

硅基互补型金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)场效应晶体管工艺已经发展到了14 nm技术节点,预计将很快到达其极限,需要寻找新的信息器件来延续摩尔定律.由于具备超小尺寸、高迁移率等显著优点,碳纳米管被认为是后摩尔时代最有潜力替代硅作为晶体管沟道的纳米材料之一.经过近20年的研究,基于碳纳米管场效应晶体管的技术已经取得了巨大的进步.本文将回顾碳纳米管场效应晶体管领域的关键性技术,包括N型欧姆接触实现、"无掺杂"CMOS技术、自对准顶栅结构以及尺寸缩减技术等.而且我们将分析碳纳米管晶体管在大规模材料制备以及碳管和电极接触方面存在的问题,并提出可能的解决方案.在此基础上,通过分析实验数据和模拟结果,对碳纳米管电子学的未来发展做出预测和展望,结果表明碳纳米管晶体管的潜力巨大,通过对材料和器件结构进行合理优化,碳纳米管晶体管在性能上可能远远超过硅基半导体对应技术节点的晶体管,成为后摩尔时代极其具有竞争力的信息器件.     

聚焦离子束加工单晶金刚石的亚表层损伤研究

为保证聚焦离子束(FIB)制造微细零部件或微刀具等的加工表面使用性能和使用寿命,研究了使用FIB技术加工单晶金刚石超硬材料的亚表层损伤。从粒子碰撞和能量交换两种角度分析了FIB加工亚表层损伤的形成原理,利用SRIM软件模拟了FIB加工单晶金刚石的离子轰击过程,确定了FIB亚表层损伤区域横截面半径,以及亚表层损伤深度。研究表明,理论上FIB加工金刚石靶材,其亚表层损伤截面半径不超过微米级零部件特征尺寸的2%,损伤深度不超过1%。     

FPGA中的非挥发布线开关元素——Flash开关技术的研究

采用ISE器件模拟软件对Flash(快闪)开关进行建模和仿真.通过仿真结果,论证了Flash开关在速度和速度面积乘积上具有优势,可以代替NMOS导通晶体管作为FPGA(现场可编程门阵列)中的布线开关.同时还给出了提高Flash开关性能的方法及在3.3V单电源供电条件下的应用方案.     

基于SET/MOS混合结构的奇偶校验码产生电路的设计

基于单电子晶体管(SET)的库仑振荡效应和多栅输入特性,利用SET和金属氧化物半导体场效应晶体管(MOS管)的互补特性,设计了基于SET/MOS混合电路的奇偶校验码产生电路.利用HSPICE对所设计电路进行仿真验证,结果表明,该电路能够实现产生奇偶校验码的功能.该SET/MOS混合电路的实现只需要1个PMOS管、1个N...     

A III-V nanowire channel on silicon for high-performance vertical transistors

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.     

Carbon Nanotube Transistor with Short-Term Memory

Short-Term Memory(STM) is a primary capability of the human brain. Humans use STM to remember a small amount of information, like someone’s phone number, for a short period of time. Usually the duration of STM is less than 1 minute. Synapses, the connections between neurons, are of vital importance to memory in biological brains. For mimicking the memory function of synapses, Carbon Nanotube(CNT) networks based thinfilm transistors with Electric Double Layers(EDL) at the dielectric/channel interface were researched in this work.A response characteristic of pre-synaptic potential pulses on the gate electrode of this CNT synaptic transistor was shown remarkably similar to Excitatory Post-Synaptic Current(EPSC) of biological synapses. Also a multi-level modulatable STM of CNT synaptic transistors was investigated. Post-synaptic current was shown with tunable peak values, on-off ratio, and relaxation time.     

Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal-oxide-semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.     

Academic and industry research progress in germanium nanodevices

Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.     

石墨烯场效应晶体管的光响应特性研究

采用电子束曝光和剥离工艺制备石墨烯场效应晶体管, 并研究其光电响应特性。结果表明, 当激光光斑(波长为633 nm)照射在金属电极边缘的石墨烯沟道时, 可测得明显的光电流。背栅电压能够有效调制光电响应, 可以改变光电流的大小和方向。在背栅调控下, 光电流出现饱和现象, 石墨烯晶体管的光响应度最大达到46.5 μA /W,可用于构建基于石墨烯的新型光探测器。     

新型低泄漏防闩锁ESD钳位保护电路

提出了一种新型抗静电泄放(ESD)钳位保护电路--栅控可控硅级联二极管串(gcSCR-CDS)结构.相比传统级联二极管串(CDS)结构,新结构利用插入的SCR管减小了钳位电路的泄漏电流和导通电阻,提高了电路的抗ESD能力;利用栅控的PMOS管,提高了维持电压,抑制了闩锁效应.0.35μm标准CMOS工艺流片结果表明,该结构泄漏电流为 12nA,抗ESD能力超过 8kV.     

新型垂直沟道的NPN型偶载场效应晶体管的设计及特性

研制了一种新模式的半导体场效应晶体第－－垂直沟道的偶载场效应晶体管（VDCFET），这种结构可以避免现有光刻技术的制约，使用常规的半导体双极晶体管工艺，既可把有效沟道长度减短，大大提高器件的速度，又可将电源电压降低到小于1V，大幅度降低功耗，改进其电学性能。本器件可应用于高频电路、D触发器、环振电路及反相器等重要电路。从纵向和横向报道了器件的设计思想，并给出了器件特性的测量结果。