Hardware Euclidean Distance Transform Implementation

Based on an efficient algorithm of Euclidean distance transform for binary images, a circuit of O (N^2) size is proposed. With in-place calculation, both the intermediate data storing and the result output use the same menmory with the input data. This reduces the amount of menmory largely. By replacing multipliers with coumters, comparators, and adders, the circuit size is further reduced and its calculation speed is improved also.     

Effect of Processing Conditions on the Interlaced Yarn

A new interlacer is used in this paper to investigate the effect of processing conditions on the properties of interlaced yarn. The experimental results show that number of tangles of interlaced yarn changes little with air pressure from 0.2 MPa to 0.5 MPa, and the number of tangles has a maximum value with yarn speed changing. For two yarn directions of entering and leaving yarn guide of interalcer, the yarn speed for the maximum number of tangles is 400 m/rain and 600 m/rain, respectively. The number of tangles changes with air pressure and yarn speed for two yarn directions is compared.     

Development and study on automatic balancer based on counter weight by magnetic force

Rotating machines are very sensitive to mass unbalance which has a harmful effect on its running accuracy and service life. Therefore,a variety of dynamic balancing methods and devices are studied to reduce the vibration caused by mass unbalance. On-line active balancing is a new balancing procedure which is more convenient and precise than the previous methods. In this paper,an electromagnetic balancer based on ring coils and permanent magnets is presented. The balancer has a simple structure and the self-locking function without clutch,and transfers power by the non-contact electromagnetic field. In order to justify the rationality of its design,a two-dimension(2D) electromagnetic finite element model is conducted to verify that this magnetic circuit has no flux leakage and saturation. A three-dimension (3D) 1/10 model of the balancer is built to obtain the self-locking torque and driving torque. Based on the research work above,an electromagnetic balancer is developed. By testing the balancer using COCO80,it is verified effective to reduce the rotor unbalance at the speed of 1300 r/min.     

FIDER： A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan

As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.     

A 65-nm 1-Gb NOR floating-gate flash memory with less than 50-ns access time

This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory, in which the cell device and chip circuit are developed and optimized. In order to solve the speed problem of giga-level NOR flash in the deep submicron process, the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estimated. Based on that, the read path and key modules are optimized to enhance the chip access property and reliability. With the measurement results, the flash memory cell presents good endurance and retention properties, and the macro is operated with 1-las/byte program speed and less than 50-ns read time under 3.3 V supply.     

Design and implementation of control system for superconducting RSFQ circuit

The superconducting rapid single flux quantum(RSFQ) integrated circuit is a promising solution for overcoming speed and power bottlenecks in high-performance computing systems in the postMoore era. This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology. Since superconducting microprocessors, which operate at cryogenic temperatures, require support from semiconductor circuits, the proposed desi...     

Dynamics of high speed wheel/rail system and its modelling

With the fast increasing of train speed the interactions among the train,the track,and the power cate-nary system become very strong. Such interactions are also strongly coupled with the action of high speed airflow due to the high speed running. Hence,the existing research methods and numerical al-gorithms of railway vehicle/track systems are not fully available for characterizing the transient dy-namic and long-term behaviors of train/track at higher speed. The present paper reviews the existing studies on coupling dynamics of railway vehicle/track,and clarifies their advantages and disadvan-tages and then puts forward an innovation stratagem for high speed railway based on rolling contact of wheel/rail systems. In the innovation stratagem,a comprehensive dynamic model of wheels/rails sys-tems is developed to simultaneously consider the track system,the train,the rolling contact of wheel/rail,the catenary/pantograph system,and the high speed airflow with the train. The motion equations of the subsystems and their coupling boundaries are given and discussed. For the reliability and safety of the high speed train in service,the long-term behavior of the structures of the train and the track is considered in the comprehensive model. Moreover,a generalized failure model,consider-ing the structures and the materials and working in the comprehensive dynamic model of wheels/rails system,as well as the simulation system of structure failure of the high speed train/track is established. Consequently,the present studies on the dynamics of the coupled vehicle/track will be further and largely extended.     

Modeling and Optimization of Stand-Alone Hybrid Power System: a Case Study for a Household in Urumqi,China

In order to alleviate environmental pollution of Urumqi,China,a stand-alone hybrid wind / PV / battery power system was studied for this region. An accurate structure and model of the standalone hybrid wind / PV / battery power system for a household in that region was presented in this study. On the basis of wind speed,solar radiation,ambient temperature,and load data,the optimal design of the hybrid system is determined using a genetic algorithm( GA). As a result,the optimal hybrid system for a household consists of one wind turbine,21. 407 6 m~2 of PV arrays,and 20. 958 kW ·h of battery bank capacity. The system has a loss of power supply probability( LPSP) of 0. 019 9 and the minimum total annualized cost is $ 35 333.     

Optimizing Work Zones for Two-Lane Urban Road Maintenance Projects

Road maintenance work brings costs to the government and delays to users. The setting up of work zones often leads to severe congestion during peak hours, especially in busy urban areas. A road maintenance delay model is presented here that includes consideration of excessive traffic flow and non-motorists. Atrial-and-error method is used to find the optimal work zone length and the best work starting time to minimize the total cost of maintenance and delays. A numerical example with a sensitivity analysis is also given. The results show that optimal starting time is not sensitive to the flow speed and the increase of work zone speeds sharply reduces the total cost when the road is congested.     

Layered Multi-mode Optimal Control Strategy for Multi-MW Wind Turbine

The control strategy is one of the most important renewable technology, and an increasing number of multi- MW wind turbines are being developed with a variable speed-variable pitch （ VS-VP ） technology. The main objective of adopting a VS-VP technology is to improve the fast response speed and capture maximum energy. But the power generated by wind turbine changes rapidly because of the continuous fluctuation of wind speed and direction. At the same time, wind energy conversion systems are of high order, time delays and strong nonlinear characteristics because of many uncertain factors. Based on analyzing the all dynamic processes of wind turbine, a kind of layered multi-mode optimal control strategy is presented which is that three control strategies： bang-bang, fuzzy and adaptive proportional integral derivative （PID） are adopted according to different stages and expected performance of wind turbine to capture optimum wind power, compensate the nonlinearity and improve the wind turbine performance at low, rated and high wind speed.     

A New Method for the Detections of Multiple Faults Using Binary Decision Diagrams

With the complexity of integrated circuits is continually increasing, a local defect in circuits may cause multiple faults. The behavior of a digital circuit with a multiple fault may significantly differ from that of a single fault. A new method for the detection of multiple faults in digital circuits is presented in this paper, the method is based on binary decision diagram （BDD）. First of all, the BDDs for the normal circuit and faulty circuit are built respectively. Secondly, a test BDD is obtained by the XOR operation of the BDDs corresponds to normal circuit and faulty circuit. In the test BDD, each input assignment that leads to the leaf node labeled 1 is a test vector of multiple faults. Therefore, the test set of multiple faults is generated by searching for the type of input assignments in the test BDD. Experimental results on some digital circuits show the feasibility of the approach presented in this paper.     

24-bit Low-Power Low-Cost Digital Audio Sigma-Delta DAC

This paper describes a low-power low-cost 24-bit Σ-digital-to-analog converter (DAC) for portable digital-audio applications.The interpolation filter uses a no-multiplier scheme to implement the arithmetic units and reading-writing common storage scheme for the delay-line to significantly reduce the die area.A 15-level quantizer,third-order,single-stage Σ-modulator is employed to reduce the passband quantization noise,relax the out-of-band filtering requirements,and enhance immunity to clock jitter.A data weighted averaging algorithm is used to mitigate the nonlinearity caused by capacitor mismatch.A direct charge transfer switched-capacitor low-pass filter (DCT-SC LPF) is used to reconstruct the analog signal to reduce the kT/C noise and capacitor mismatch effect with a small increase of the power dissipation.The chip was fabricated in the SMIC 0.13 μm 1P5M CMOS process.The cell area of the digital part is 0.056 mm 2 and the total area of the analog part is 0.34 mm 2.The supply voltage is 1.2 V for the digital circuit and 3.3 V for the analog circuit.The power consumption of the analog part is 3.5 mW.The audio DAC achieves a 100 dB dynamic range and an 84 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband.The results show that these performances are good enough for high quality portable audio applications.     

Improve Fractal Compression Encoding Speed Using Feature Extraction and Self-organization Network

Image compression consists of two main parts: encoding and decoding. One of the important problems of the fractal theory is the long encoding implementation time, which hindered the acceptance of fractal image compression as a practical method. The long encoding time results from the need to perform a large number of domain-range matches, the total encoding time is the product of the number of matches and the time to perform each match. In order to improve encoding speed, a hybrid method combining features extraction and self-organization network has been provided, which is based on the feature extraction approach the comparison pixels by pixels between the feature of range blocks and domains blocks. The efficiency of the new method was been proved by examples.     

Influence of operation parameters on flash smelting furnace based on CFD

The influence of three important operation parameters in Jinlong flash smelting furnace, including the distributing blast speed, the oxygen enrichment rate of process air and the ratio of central oxygen to overall oxygen (O_c/O_o), has been investigated using a virtual simulation system on copper flash smelting furnace. The core of this virtual simulation system is a numerical simulation of CFD (computational fluid dynamics), and this system incorporates coupling momentum transport, heat transport, mass transport,reaction kinetics between gas and particles and chemical reactions between gas and gas. A set of numerical predicted data were obtained. The CFD simulation shows that there is a sensitive zone of the distributing blast speed, and the dust content ascends when the speed exceeds 180 m·s-1. Increasing the oxygen concentration of processing air benefits the efficient production of the flash smelting furnace.     

Realization of a tunable analog predistorter using parallel combination technique for laser driver applications

This paper describes a new approach for designing analog predistorters that can compensate for the nonlinear distortion of laser drivers in a radio-over-fiber(RoF) system.In contrast to previous works,this paper analyzes the transfer characteristics of CMOS transistors,by combining parallel currents of CMOS transistors in various W/L and negative bias voltages to realize the tunable analog predistortion function.The circuit is fabricated by a standard 0.18μm CMOS technology.The core circuit current consumption is only 15 mA and the entire driver circuit works in a band-pass from 1 ~2.2GHz.Experimental results of two-tone tests have shown that with an analog predistortoer the IIP3 of the laser driver circuit has an improvement of 4.91 dB.     

Kite code-based incremental redundancy hybrid ARQ scheme for fast-fading channels

Incremental redundancy hybrid automatic repeat request （IR HARQ） has been extensively studied for reliable data transmission over slow-fading or quasi-static channels. With the increase in movement speed of users and the use of long code words for data transmission, IR HARQ strategy in fast-fading channels is starting to attract attention in the academia. This paper studies the perfor- mance of the IR HARQ strategy based on Kite codes （a class of rateless codes） in the finite regime over fast-fading channels where a number of channel realizations are experienced in each retransmission round. We propose an algorithm that exploits current decoding reliability to determine the size of subsequent retransmissions. Long- term throughput and delay constraint throughput are ana- lyzed and compared. Furthermore, in HARQ systems available, most of the computation power is consumed on failed decoding if a code word is retransmitted many times, which is not energy-efficient. Therefore, to improve theenergy efficiency, we propose two efficient algorithms （early stopping algorithm and freezing node algorithm） for incremental decoding, which reduce the computational complexity of the most time-consuming steps in decoding procedure. Simulation results show that the substantial complexity reduction is achieved in terms of the total required number of decoding iterations and the required node operation complexity compared to conventional incremental decoding scheme.     

Leaching of vanadium,sodium, and silicon from molten V-Ti-bearing slag obtained from low-grade vanadium-bearing titanomagnetite

The water leaching process of vanadium, sodium, and silicon from molten vanadium-titanium-bearing (V-Ti-bearing) slag obtained from low-grade vanadium-bearing titanomagnetite was investigated systematically. The results show that calcium titanate, sodium aluminosilicate, sodium oxide, silicon dioxide and sodium vanadate are the major components of the molten V-Ti-bearing slag. The experimental results indicate that the liquid-solid (L/S) mass ratio significantly affects the leaching process because of the respective solubilities and diffusion rates of the components. A total of 83.8% of vanadium, 72.8% of sodium, and 16.1% of silicon can be leached out via a triple counter-current leaching process under the optimal conditions of a particle size below 0.074 mm, a temperature of 90°C, a leaching time of 20 min, an L/S mass ratio of 4:1, and a stirring speed of 300 r/min. The kinetics of vanadium leaching is well described by an internal diffusion-controlled model and the apparent activation energy is 11.1 kJ/mol. The leaching mechanism of vanadium was also analyzed.     

Numerical Simulation of Gas-Solid Two-Phase Flow in Reverse Blowing Pickup Mouth

Pickup mouth is a key component for the service performance of a street sweeper. Computational fluid dynamics( CFD) technology,as an analysis tool in fluid flow simulation,is employed in this work because it can greatly shorten the design period. To obtain higher simulation accuracy,the gas-solid coupling inside the process cannot be neglected during numerical simulation.Our optimization procedure considers the influence of structure and operational parameters. It is recommended that the outlet diameter is less than 0. 42 of the width and the outlet inclination angle is 110°for structure parameters. The dust collection efficiency is improved when the reverse flow rate is 70% of the total volume,the sweepertraveling speed is 10 km / h,and the pressure drop is 2 400 Pa.Simulation results exhibit well consistency with the physical experimental results.     

A Novel Design of Power management integrated circuit with 90 plus efficiency used in AC/DC converter

Recently, resonant AC/DC converter has been accepted by the industry. However, the efficiency will be decreased at light load. So, a novel topology with critical controlling mode combined with resonant ones is proposed in this paper. The new topology can correspond to a 90 plus percent of power converting. So，a novel topology of an state of art integrated circuit, which can be used as power management circuit, has been designed based on the above new topology. A simulator which is specifically suitable for the power controller has been founded in this work and it has been used for the simulation of the novel architecture and the proposed integrated circuit.     

Minimizing crosstalk for high-speed and high-density bus systems using the sample-decision method

This paper presents a method based on a sample-decision （SD） circuit to suppress crosstalk and noise for a high-speed and high-density bus system. A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates （BERs） formula is giv- en by the SD circuit. It is shown that for long transmission line systems, multiple SD circuits can improve the BERs significantly. Circuits simulation for single SD method is also done, it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones, they will be eliminated completely for the cases investigated.