高浓度弛豫SiGe/SOI材料的制备研究

对SOl（绝缘体上的硅）衬底上外延生长的SiGe层进行了研究，并利用透射电镜、AES、Raman光谱、X-ray多晶衍射等技术对SiGe／SOI材料做了表征。结果表明：制备的材料中Ge／Si元素分布均匀，SiGe层是高度弛豫的，SiGe层中应变通过产生失配位错被释放出来。     

Investigation of silicon on insulator fabricated by two-step O+ implantation

In this paper, we investigated the dose window of forming a continuous buried oxide (BOX) layer by single implantation at the implantation energy of 200 keV. Then, an improved two-step implantation process with second implantation dose of 3×10¹⁵ cm^?2 was developed to fabricate high quality separation by implanted oxygen (SIMOX) silicon on insulator (SOI) wafers. Compared with traditional single implantation, the implantation dose is reduced by 18.2%. In addition, the thickness and uniformity of the BOX layers were evaluated by spectroscopic ellipsometry. Defect-free top Si as well as atomic-scale sharp top Si/buried oxide interfaces were observed by transmission electron microscopy, indicating a high crystal quality and a perfect structure of the SOI fabricated by two step implantation. The top Si/BOX interface morphology of the SOI wafers fabricated by single or two-step implantation was also investigated by atomic force microscopy.     

原位生成法半固态连接Si3N4复相陶瓷的接头组织

为探索陶瓷材料的有效连接途径,提出一种原位生成增强颗粒的半固态钎焊陶瓷材料方法。采用自制钎料对Si3N4复相陶瓷进行钎焊试验。采取分步焊接的方法,在1023K下使钎缝内生成一定数量的AlCu2Ti金属间化合物,然后在1173K下对陶瓷材料进行半固态连接。显微观察表明:钎缝组织由低熔点的钎料基体和高熔点的金属间化合物组成,金属间化合物均匀分布在钎料基体中,有利于改善接头性能,降低接头的热膨胀不均匀性。     

环境友好半导体材料Ca2Si的研究进展

Ca2Si是由两种丰富且无毒的化学元素构成,被认为是很有前景的新型环境半导体材料之一。文章综述了近年来Ca2Si的晶格特性、光电性质及其制备方法的研究进展,并着重对两步法制备Ca2Si薄膜进行了介绍,最后展望了Ca2Si的应用前景,探讨了当前Ca2Si研究领域中存在的问题。     

Si/Si低温键合界面的XPS研究

利用金属过渡层的方法实现了Si/Si低温键合.拉力测试表明,温度越高,键合强度越大.采用X射线光电子能谱对Si/Si键合界面进行了研究,结果表明,退火样品的界面主要为Au-Si共晶合金;Si-Au含量比随着退火温度的升高和刻蚀深度的增加而增大.     

Electronic transport in nanometre-scale silicon-on-insulator membranes

The widely used 'silicon-on-insulator' (SOI) system consists of a layer of single-crystalline silicon supported on a silicon dioxide substrate. When this silicon layer (the template layer) is very thin, the assumption that an effectively infinite number of atoms contributes to its physical properties no longer applies, and new electronic, mechanical and thermodynamic phenomena arise, distinct from those of bulk silicon. The development of unusual electronic properties with decreasing layer thickness is particularly important for silicon microelectronic devices, in which (001)-oriented SOI is often used. Here we show--using scanning tunnelling microscopy, electronic transport measurements, and theory--that electronic conduction in thin SOI(001) is determined not by bulk dopants but by the interaction of surface or interface electronic energy levels with the 'bulk' band structure of the thin silicon template layer. This interaction enables high-mobility carrier conduction in nanometre-scale SOI; conduction in even the thinnest membranes or layers of Si(001) is therefore possible, independent of any considerations of bulk doping, provided that the proper surface or interface states are available to enable the thermal excitation of 'bulk' carriers in the silicon layer.     

空间辐射效应防护的标准单元库设计与实现

为提高空间环境下电子设备的可靠性,提升抗辐射加固SOI(Silicon on Insulator)集成电路的设计效率,通过构建完整的建库流程,自主设计开发了基于33 V 035 μm PD（Partly） SOI CMOS(Complementary Metal-Semiconductor)工艺平台,并面向Synopsys电子设计自动化软件的抗辐射加固标准单元库。标准单元采用H型栅及源漏非对称注入结构,以提高抗辐射性能,最后对该单元库进行了电子设计自动化工具流程验证和测试验证。实验结果表明,检错纠错验证电路功能符合设计要求,抗总剂量水平大于300 krad (Si)。     

Si和Al对机械合金化合成Ti_3SiC_2的影响

采用3Ti/Si/2C单质粉体为原料,进行机械合金化,以合成Ti3SiC2粉体.研究了Al和过量Si对机械合金化合成Ti3SiC2的影响.研究结果表明,机械合金化单质混合粉体,会诱发自蔓延反应.反应后产生大量坚硬的颗粒状产物.机械合金化3Ti/Si/2C粉体,会产生组成相为TiC、Ti3SiC2、TiSi2和Ti5Si3的粉体与颗粒产物.添过量Si并不会促进机械合金化反应合成Ti3SiC2.添适量Al可消除硅化物,明显促进反应合成Ti3SiC2.采用3Ti/Si/2C/0.15A1粉体作原料时,颗粒产物中Ti3SiC2含量最高,为92.8wt%;而采用3Ti/Si/2C/0.20A1粉体作原料时,粉体产物中Ti3SiC2含量最高,为61.9wt%.     

Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors

Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied: such devices combine the high mobility of III-V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored-but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO(2) substrates. As a parallel with silicon-on-insulator (SOI) technology, we use 'XOI' to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO(x) layer (~1?nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6?mS?μm(-1) at a drain-source voltage of 0.5?V, with an on/off current ratio of greater than 10,000.     

机械化学还原法制备Al_2O_3-Mo_3Si/Mo_5Si_3纳米复合粉体

以MoO3、Si粉和Al粉为原料,采用机械化学还原法制备了Al2O3-Mo3Si/Mo5Si3纳米复合粉体.利用X射线衍射(XRD)、激光粒度分析仪(LPS)、透射电子显微镜(TEM)、扫描电子显微镜(SEM)和差热-热重分析(DTA-TG)等对复合粉体和球磨过程中粉体的固态反应过程进行表征.结果显示,MoO3-Si-Al混合粉体球磨5h后转变为Al2O3-Mo3Si/Mo5Si3复合粉体,反应为机械诱导的自蔓延反应.球磨20h后,Mo3Si、Mo5Si3和Al2O3的晶粒尺寸分别为27.5、23.3和31.8nm,产物具有纳米晶结构,粉体平均粒度为3.988μm,颗粒呈球形,分布均匀.DTA分析表明,复合粉体在机械化学反应过程中首先发生MoO3和Al之间的铝热反应,之后将发生一系列Mo和Si之间的反应,生成Mo5Si3和Mo3Si.