| 一种基于模拟退火的LUT结构FPGA工艺映射算法 |
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| 引用本文： | 张明,温宇杰,童家榕.一种基于模拟退火的LUT结构FPGA工艺映射算法[J].复旦学报(自然科学版),2005,44(6):951-955. |
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| 作者姓名： | 张明 温宇杰 童家榕 |
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| 作者单位： | 复旦大学,专用集成电路与系统国家重点实验室,上海,200433 |
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| 摘 要： | SoPC中提供给FPGA IP核的有限面积使面积优化成为工艺映射的关键目标之一．减少实现电路功能的可编程逻辑单元数可以有效地减小所需芯片面积，还能降低对布线资源的需求．利用模拟退火算法从全局范围对LUT结构FPGA的工艺映射过程进行考虑，针对减少所用LUT数目的目标得出映射结果，实验结果表明用该算法可以快速地得出非常优化的结果．
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| 关 键 词： | 半导体技术 现场可编程门阵列 工艺映射 查询表 模拟退火 |
| 文章编号： | 0427-7104（2005）06-0951-05 |
| 收稿时间： | 09 2 2004 12:00AM |
| 修稿时间： | 2004-09-02 |
LUT-based FPGA Technology Mapping: A Simulated Annealing Approach |
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| ZHANG Ming,WEN Yu-jie,TONG Jia-rong.LUT-based FPGA Technology Mapping: A Simulated Annealing Approach[J].Journal of Fudan University(Natural Science),2005,44(6):951-955. |
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| Authors: | ZHANG Ming WEN Yu-jie TONG Jia-rong |
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| Abstract: | Limited area provided to the field programmable gate array(FPGA) intellectual property(IP) cores in system on programmable chip(SoPC) makes area optimization a critical goal of technology mapping.Reducing the number of programmable logic units can effectively decrease the chip area needed.A simulated annealing algorithm is proposed to solve the look up table(LUT) based FPGA technology mapping problem.Experimental results show that this method results in very good optimization quickly. |
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| Keywords: | semiconductor technolcgy FPGA technology mapping LUT simulated annealing |
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