| 基于步进和量化调整的数字锁相法快速位同步 |
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| 引用本文： | 张昆.基于步进和量化调整的数字锁相法快速位同步[J].科学技术与工程,2011,11(11). |
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| 作者姓名： | 张昆 |
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| 作者单位： | 西安机电信息技术研究所,西安,710065 |
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| 摘 要： | 针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。该方法在FPGA平台上，通过综合使用步进和量化两种方式，来控制每个工作周期中分频器的脉冲调整数量，利用本地高频时钟进行二级分频得到输出的位同步信号。仿真结果表明基于FPGA的位同步系统能够稳定、快速的完成位同步功能，在保证系统稳定性的同时，值极大地缩短了系统的同步建立时间。
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| 关 键 词： | 数字锁相环 快速位同步 FPGA |
| 收稿时间： | 1/14/2011 5:17:30 PM |
| 修稿时间： | 1/26/2011 2:15:56 PM |
Fast Bit Synchronization of Digital Phrase Lock Adjusted by Step and Quantified |
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| zhangkun.Fast Bit Synchronization of Digital Phrase Lock Adjusted by Step and Quantified[J].Science Technology and Engineering,2011,11(11). |
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| Authors: | zhangkun |
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| Institution: | ZHANG Kun,GUI Yan-ning,YANG Yan,HU Jian-jun(Xi'an Institute of Electromechanical Information Technology,Xi'an 710065,P.R.China) |
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| Abstract: | Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem , proposed a method for FPGA-based realization method of fast bit synchronization. It worked in two ways by step and quantified, for changing in each work cycle to adjust the pulses number of divider. Twice divided the local high-frequency clock to output the synchronization signal. Programmed with VerilogHDL. Designed the modules, complied and simulated in ISE. The simulation result presents this method can realize fast bit synchronization. |
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| Keywords: | DPLL Fast Bit Synchronization FPGA |
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