一种低复杂度LDPC译码器的FPGA设计与实现

利用切比雪夫多项式良好的逼近性，提出了基于切比雪夫多项式拟合的BP译码算法，并将该算法在FPGA上进行了实现.该算法利用切比雪夫多项式拟合算法对传统BP算法中的复杂函数进行拟合，用少量的乘法和加法运算代替传统BP算法中的复杂函数.此外，调整得到的多项式系数，使其便于硬件实现.同时，提出一种基于移位运算的切比雪夫结构，减小因乘法器的实现带来的复杂度；并提出基于流水线设计的半并行结构，设计并实现了低复杂度的BP译码器.实验结果表明，相比于相关工作，这种结构能有效减少硬件资源.

A FPGA Design and Implementation of Low-complexity Decoder for LDPC Code

Taking advantage of the good approximation performance of Chebyshev polynomial, this paper proposed a BP algorithm based on Chebyshev polynomial fitting. And this method can transform the complicated index formula into polynomial, which can reduce the consumption of memory resources. At the same time, a Chebyshev structure with shift operation was proposed to reduce the complexity brought by multiplier; also a semi-parallel architecture with pipeline design was proposed to reduce the complexity of BP decoder. The experimental results show that such a structure can effectively reduce the hardware resources.