Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization

A 4 Mb embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory was developed with a 0.18 μm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read speed. The charge distribution was analyzed to optimize the programming and erase conditions considering both the operating speed and the endurance performance. The final test chip has a good endurance of 105 cycles and a data retention time of at least 10 years.     

一种EEPROM存储单元的读出电流检测电路

针对电可擦除编程存储器(EEPROM)存储单元的读出电流需要被精确检测的问题,该文提出了一种对EEP-ROM存储单元进行工作电流检测的电路,该电路主要用电流镜来搭建,和读出电路中的灵敏放大器相连。在检测时用电流镜电路把灵放的读出电流镜像到电流检测的输出端。模拟结果显示,用这种检测电路来检测读出电流可以取得较高的精度(98.5%)。同时,电路本身结构简单,在实际中易实现。     

基于共享技术的电荷泵电路

为了减少芯片面积,提高电荷泵的增益,提出一种基于共享技术的电荷泵电路。通过改变两个子电荷泵的串并连接关系,既可以产生一种电压较高而电流驱动能力较小的负高压,也可以产生一种电压较低但是电流驱动能力很大的负高压,这不仅满足了系统在编程和擦除时对高压的不同需求,而且还节省了大约50%的芯片面积。电荷泵电路还采取了对其中P型M O S管的衬底电压进行动态控制的方法。模拟结果表明,该电荷泵的增益提高了大约14%。该电路特别适用于需要两种以上负高压以完成编程和擦除操作的快闪存储器。     

嵌入式闪存适用的新型低压高效率电荷泵电路

随着片上系统(SoC)电源电压的降低,嵌入式快闪存储器内部电荷泵电路的电压增益不断下降.为提高低电源电压下电荷泵电路的效率,提出了一个基于两路互补结构的高效率电荷泵电路,并设计了栅压提高电路与衬底调节电路,二者的共同作用可以有效地减少传输电压的损失,提高电荷泵电路的电压增益.模拟结果表明:当电源电压为1.5V时,相比于...     

Performance and Reliability of Multilayer Silicon Nanocrystal Nonvolatile Memory

Nonvolatile memories (NVMs) with triple layers of silicon nanocrystals were fabricated with conventional CMOS technology.This paper explores the program/erase performance and reliability of NVMs with three layers of nanocrystals.The results indicate that the nanocrystals in the triple-layer nanocrystal NVM (NCNVM) are difficult to fully charge during the programming process.The programming speed of the triple-layer NCNVMs is quicker than that of single-layer NCNVMs,which means that the second and third layers of nanocrystals in the triple-layer NCNVM affect the charge of the first layer nanocrystals.Reliability tests show that the memory window has little degradation after 1×104 cycles.     

Trapped Electron and Hole Distribution Mismatch Induced Reliability Degradation of SONOS Type Memory Devices

The reliability of silicon-oxide-nitride-oxide-silicon (SONOS) type memories was analyzed using the charge pumping method and Ⅰ-Ⅴ tests at different temperatures to study its endurance and retention characteristics.A simple model was used to explain the charge loss phenomenon,with a dual-erasure method developed to improve the endurance and retention characteristics.The results indicate that the coexistence of injected holes and electrons after long term cycling,referred to as the mismatch problem,leads to degradation of the device characteristics.With the dual-erasure method,the threshold voltage,VT,window is maintained after 1×104 programming and erasing cycles and the charge loss is reduced by 410 mV after 72 h baking at 120℃.