H.264/AVC编码器中运动估计的低代价VLSI实现

通过对运动估计算法进行优化, 提出一种应用新型存储结构的流水线实现结构。通过采用合适的搜索策略、高效的率失真优化代价计算和插值部件、创新的存储结构及优化的数据流调度, 实现具有低硬件代价和存储访问的快速运动估计。该设计在SMIC 130 nm工艺下综合, 时钟频率可达到167 MHz, 消耗181.7 K逻辑门和13.8 KB存储, 相比同类设计具有更高的硬件效率。该设计集成在一个H.264/AVC编码器中进行FPGA原型验证和VLSI实现。 SMIC 65 nm工艺下, 整个芯片面积为1.74 mm×1.74 mm, 工作频率为350 MHz, 可以支持实时高清(1080P@60fps)编码。     

Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC)

This paper evaluates the Triplet Based Architecture, TriBA – a new idea in chip multiprocessor architectures and a class of Direct Interconnection Network (DIN). TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized. Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We propose a new criterion in performance evaluation that is based on the concept of locality in an interconnection network, the “lower layer complete connect”. Our proposed criterion depicts how completely a processing node is connected to all its neighbors. TriBA is compared with 2D Mesh and Binary Tree as static interconnection network. The comparison / evaluation is enumerated from three orthogonal view points, viz., computational speed, physical layout and cost. Our analysis concludes that TriBA is computationally efficient interconnection strategy that exploits group locality in processing nodes.     

基于剩余率失真信息的码率控制算法及其VLSI结构设计

引入JPEG2000图像片编码的实时剩余率失真信息,并用它和当前编码通道的率失真斜率在编码过程中判定当前编码通道是否被截断,使得Tier1编码和码流截断并行。最后还设计本算法的VLSI体系结构。实验结果表明：本算法在编码过程中实时截断编码码流,实时性高,资源损耗小;并且重建图像质量高。     

一种H.264／AVC解码器关键技术的设计

本文提出了H.264/AVC解码器的系统结构及其核心单元总体结构的设计研究方案.重点包括系统的流水线设计、双总线设计以及IDCT变换、帧内预测、帧间运动补偿等关键模块的设计与大规模逻辑实现.硬件解码部分在200 MHz 系统时钟时可以实时解码H.264 High 4:4:4 profile 4.0 level码流.     

Random testing for system-level functional verification of system-on-chip

In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed. The validity of this method is proven theoretically. Specifically, testcases are generated according to many approaches of randomization. Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language. Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily. The comparison method is put to use in the evaluation approach of the testing validity. The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing. The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.     

MPEG-2视频反量化和IDCT的VLSI设计

反量化（ＩＱ）和反离散余弦变换（ＩＤＣＴ）是ＭＰＥＧ－２中恢复帧内编码系数或差分系数的重要手段。设计了用于ＭＰＥＧ－２ＭＰ＠ＭＬ视频解码超大规模集成电路（ＶＬＳＩ）的ＩＱ和ＩＤＣＴ电路结构,采用ＶＨＤＬ进行描述并通过模拟得到验证。采用全硬件实现的方法,并针对性地提出了相应的硬件电路结构设计,减少了电路规模以适应ＭＰＥＧ－２ＭＰ＠ＭＬ视频较大的数据量,达到了实时解码的目的。     

一种适用无线视频通讯低复杂度H.264 VBSME VLSI结构

针对无线视频通讯H.264编码器关键技术VBSME VLSI实现,提出了一种低复杂度结构,该结构由宏块输入缓存器,17×16 蛇形扫描寄存器阵列, 8×8 PE阵列,4×4 SAD加法树和四步可变块运动矢量生成器组成。在有效保持所有的H.264宏块特性的基础上,相对于宏块级的VBSME结构,通过采用新提出的四步可变块运动矢量生成器和双时钟频率调谐技术,主要的数据通道宽度缩减到25%, 硬件代价缩减到37％,关键路径延时由9.8?ns减少到8.2?ns,功耗约降低了50.3％。     

Low-complexity systolic architecture for inversion

A modified extended binary Euclid＇ s algorithm which is more regularly iterative for computing an inversion in GF（2^m） is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has area complexity of O（m）, latency of 5m - 2, and throughput of 1/m. Compared with other serial systolic arehiteetures, the proposed one has the smallest area complexity, shorter latency. It is highly regular, modular, and thus well suited for high-speed VLSI design.     

ASM函数的综合与分析

本文提出数字系统的ASM设计的直接综合法。借此,ASM函数用其图或表,而无需推导能够直接在合适的ROM、PLA或一组MUX模块上加以综合。ASM函数的输入是经过MUX预选后送入到综合结构上的,这样能使系统函数存贮密度减小,从而使综合结构网络简化。本法使整个算法更清晰、更系统、更简化和更有效。     

MPEG-2运动补偿的VLSI设计

基于ＭＰＥＧ－２解码中运动补偿的控制复杂、数据吞吐量大，实现较困难，提出了一种适合于ＭＰＥＧ－２ＭＰ＠ＭＬ的运动补偿硬件实现方案，解决了时序分配，输入输出控制等较难处理的问题。文中的方案已经采用ＶＨＤＬ描述，并使用电子设计自动化（ＥＤＡ）工具进行了模拟和验证。结果表明，方案满足ＭＰＥＧ－２解码的要求，可用于ＭＰＥＧ－２的ＶＬＳＩ实现。