Tuning charge transport in solution-sheared organic semiconductors using lattice strain

Circuits based on organic semiconductors are being actively explored for flexible, transparent and low-cost electronic applications. But to realize such applications, the charge carrier mobilities of solution-processed organic semiconductors must be improved. For inorganic semiconductors, a general method of increasing charge carrier mobility is to introduce strain within the crystal lattice. Here we describe a solution-processing technique for organic semiconductors in which lattice strain is used to increase charge carrier mobilities by introducing greater electron orbital overlap between the component molecules. For organic semiconductors, the spacing between cofacially stacked, conjugated backbones (the π-π stacking distance) greatly influences electron orbital overlap and therefore mobility. Using our method to incrementally introduce lattice strain, we alter the π-π stacking distance of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) from 3.33?? to 3.08??. We believe that 3.08?? is the shortest π-π stacking distance that has been achieved in an organic semiconductor crystal lattice (although a π-π distance of 3.04?? has been achieved through intramolecular bonding). The positive charge carrier (hole) mobility in TIPS-pentacene transistors increased from 0.8?cm(2)?V(-1)?s(-1) for unstrained films to a high mobility of 4.6?cm(2)?V(-1)?s(-1) for a strained film. Using solution processing to modify molecular packing through lattice strain should aid the development of high-performance, low-cost organic semiconducting devices.     

Inkjet printing of single-crystal films

The use of single crystals has been fundamental to the development of semiconductor microelectronics and solid-state science. Whether based on inorganic or organic materials, the devices that show the highest performance rely on single-crystal interfaces, with their nearly perfect translational symmetry and exceptionally high chemical purity. Attention has recently been focused on developing simple ways of producing electronic devices by means of printing technologies. 'Printed electronics' is being explored for the manufacture of large-area and flexible electronic devices by the patterned application of functional inks containing soluble or dispersed semiconducting materials. However, because of the strong self-organizing tendency of the deposited materials, the production of semiconducting thin films of high crystallinity (indispensable for realizing high carrier mobility) may be incompatible with conventional printing processes. Here we develop a method that combines the technique of antisolvent crystallization with inkjet printing to produce organic semiconducting thin films of high crystallinity. Specifically, we show that mixing fine droplets of an antisolvent and a solution of an active semiconducting component within a confined area on an amorphous substrate can trigger the controlled formation of exceptionally uniform single-crystal or polycrystalline thin films that grow at the liquid-air interfaces. Using this approach, we have printed single crystals of the organic semiconductor 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C(8)-BTBT) (ref. 15), yielding thin-film transistors with average carrier mobilities as high as 16.4?cm(2)?V(-1)?s(-1). This printing technique constitutes a major step towards the use of high-performance single-crystal semiconductor devices for large-area and flexible electronics applications.     

Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors

Transparent electronic devices formed on flexible substrates are expected to meet emerging technological demands where silicon-based electronics cannot provide a solution. Examples of active flexible applications include paper displays and wearable computers. So far, mainly flexible devices based on hydrogenated amorphous silicon (a-Si:H) and organic semiconductors have been investigated. However, the performance of these devices has been insufficient for use as transistors in practical computers and current-driven organic light-emitting diode displays. Fabricating high-performance devices is challenging, owing to a trade-off between processing temperature and device performance. Here, we propose to solve this problem by using a novel semiconducting material--namely, a transparent amorphous oxide semiconductor from the In-Ga-Zn-O system (a-IGZO)--for the active channel in transparent thin-film transistors (TTFTs). The a-IGZO is deposited on polyethylene terephthalate at room temperature and exhibits Hall effect mobilities exceeding 10 cm2 V(-1) s(-1), which is an order of magnitude larger than for hydrogenated amorphous silicon. TTFTs fabricated on polyethylene terephthalate sheets exhibit saturation mobilities of 6-9 cm2 V(-1) s(-1), and device characteristics are stable during repetitive bending of the TTFT sheet.     

Layered boron nitride as a release layer for mechanical transfer of GaN-based devices

Nitride semiconductors are the materials of choice for a variety of device applications, notably optoelectronics and high-frequency/high-power electronics. One important practical goal is to realize such devices on large, flexible and affordable substrates, on which direct growth of nitride semiconductors of sufficient quality is problematic. Several techniques--such as laser lift-off--have been investigated to enable the transfer of nitride devices from one substrate to another, but existing methods still have some important disadvantages. Here we demonstrate that hexagonal boron nitride (h-BN) can form a release layer that enables the mechanical transfer of gallium nitride (GaN)-based device structures onto foreign substrates. The h-BN layer serves two purposes: it acts as a buffer layer for the growth of high-quality GaN-based semiconductors, and provides a shear plane that makes it straightforward to release the resulting devices. We illustrate the potential versatility of this approach by using h-BN-buffered sapphire substrates to grow an AlGaN/GaN heterostructure with electron mobility of 1,100?cm(2)?V(-1)?s(-1), an InGaN/GaN multiple-quantum-well structure, and a multiple-quantum-well light-emitting diode. These device structures, ranging in area from five millimetres square to two centimetres square, are then mechanically released from the sapphire substrates and successfully transferred onto other substrates.     

High-mobility ultrathin semiconducting films prepared by spin coating

The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (approximately 50 A), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS(2-x)Se(x) films, which exhibit n-type transport, large current densities (>10(5) A cm(-2)) and mobilities greater than 10 cm2 V(-1) s(-1)--an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).     

Flexible photodetector based on large-area few-layer MoS2

Developing flexible photodetectors is crucial for both military and civil fields. Large-area MoS_2 films from several to dozens of layers are controllably synthesized via a facile atmospheric-pressure sulfurization route of predeposited Mo films and transferred onto other substrates(e.g. SiO_2/Si wafers, quartz slides, polymers). The flexible photodetectors were fabricated by transferring as-synthesized MoS_2 films onto interdigital electrodes patterned on polyethylene terephthalate(PET) substrates. No additional complex lithography positioning techniques were needed during the device fabrication process due to the large area of as-grown atomic thin MoS_2 films. As-obtained flexible photodetectors showed responsibilities of ～ 20 mA/W and response time of several seconds. This demonstrates the possibility of employing large-area two-dimensional semiconductors to meet the increasing demands for wearable and portable electronics.     

Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors

Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied: such devices combine the high mobility of III-V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored-but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO(2) substrates. As a parallel with silicon-on-insulator (SOI) technology, we use 'XOI' to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO(x) layer (~1?nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6?mS?μm(-1) at a drain-source voltage of 0.5?V, with an on/off current ratio of greater than 10,000.     

Nanotechnology: high-speed integrated nanowire circuits

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.     

Solution-processed silicon films and transistors

The use of solution processes-as opposed to conventional vacuum processes and vapour-phase deposition-for the fabrication of electronic devices has received considerable attention for a wide range of applications, with a view to reducing processing costs. In particular, the ability to print semiconductor devices using liquid-phase materials could prove essential for some envisaged applications, such as large-area flexible displays. Recent research in this area has largely been focused on organic semiconductors, some of which have mobilities comparable to that of amorphous silicon (a-Si); but issues of reliability remain. Solution processing of metal chalcogenide semiconductors to fabricate stable and high-performance transistors has also been reported. This class of materials is being explored as a possible substitute for silicon, given the complex and expensive manufacturing processes required to fabricate devices from the latter. However, if high-quality silicon films could be prepared by a solution process, this situation might change drastically. Here we demonstrate the solution processing of silicon thin-film transistors (TFTs) using a silane-based liquid precursor. Using this precursor, we have prepared polycrystalline silicon (poly-Si) films by both spin-coating and ink-jet printing, from which we fabricate TFTs with mobilities of 108 cm2 V(-1) s(-1) and 6.5 cm2 V(-1) s(-1), respectively. Although the processing conditions have yet to be optimized, these mobilities are already greater than those that have been achieved in solution-processed organic TFTs, and they exceed those of a-Si TFTs (< or = 1 cm2 V(-1) s(-1)).     

Patterning organic single-crystal transistor arrays

Field-effect transistors made of organic single crystals are ideal for studying the charge transport characteristics of organic semiconductor materials. Their outstanding device performance, relative to that of transistors made of organic thin films, makes them also attractive candidates for electronic applications such as active matrix displays and sensor arrays. These applications require minimal cross-talk between neighbouring devices. In the case of thin film systems, simple patterning of the active semiconductor layer minimizes cross-talk. But when using organic single crystals, the only approach currently available for creating arrays of separate devices is manual selection and placing of individual crystals-a process prohibitive for producing devices at high density and with reasonable throughput. In contrast, inorganic crystals have been grown in extended arrays, and efficient and large-area fabrication of silicon crystalline islands with high mobilities for electronic applications has been reported. Here we describe a method for effectively fabricating large arrays of single crystals of a wide range of organic semiconductor materials directly onto transistor source-drain electrodes. We find that film domains of octadecyltriethoxysilane microcontact-printed onto either clean Si/SiO(2) surfaces or flexible plastic provide control over the nucleation of vapour-grown organic single crystals. This allows us to fabricate large arrays of high-performance organic single-crystal field-effect transistors with mobilities as high as 2.4 cm(2) V(-1) s(-1) and on/off ratios greater than 10(7), and devices on flexible substrates that retain their performance after significant bending. These results suggest that our fabrication approach constitutes a promising step that might ultimately allow us to utilize high-performance organic single-crystal field-effect transistors for large-area electronics applications.     

Ultralow-power organic complementary circuits

The prospect of using low-temperature processable organic semiconductors to implement transistors, circuits, displays and sensors on arbitrary substrates, such as glass or plastics, offers enormous potential for a wide range of electronic products. Of particular interest are portable devices that can be powered by small batteries or by near-field radio-frequency coupling. The main problem with existing approaches is the large power consumption of conventional organic circuits, which makes battery-powered applications problematic, if not impossible. Here we demonstrate an organic circuit with very low power consumption that uses a self-assembled monolayer gate dielectric and two different air-stable molecular semiconductors (pentacene and hexadecafluorocopperphthalocyanine, F16CuPc). The monolayer dielectric is grown on patterned metal gates at room temperature and is optimized to provide a large gate capacitance and low gate leakage currents. By combining low-voltage p-channel and n-channel organic thin-film transistors in a complementary circuit design, the static currents are reduced to below 100 pA per logic gate. We have fabricated complementary inverters, NAND gates, and ring oscillators that operate with supply voltages between 1.5 and 3 V and have a static power consumption of less than 1 nW per logic gate. These organic circuits are thus well suited for battery-powered systems such as portable display devices and large-surface sensor networks as well as for radio-frequency identification tags with extended operating range.     

低电压并五苯薄膜场效应晶体管

利用全蒸镀法, 以并五苯作为有源层, 聚甲基丙烯酸甲 酯（PMMA）作为绝缘层, 制备了全有机薄膜场效应晶体管（TFT）. 测试结果表明, 器件具有较低的工作电压和较高的场效应迁移率. 对工作机理进行了探讨.     

Nanometre-scale electronics with III-V compound semiconductors

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.     

Large-scale complementary integrated circuits based on organic transistors

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of performance against transistor parameter variations are crucial. In silicon-based microelectronics, these are achieved through the use of complementary logic-which incorporates both p- and n-type transistors-and it is therefore reasonable to suppose that adoption of such an approach with organic semiconductors will similarly result in reduced power dissipation, improved noise margins and greater operational stability. Complementary inverters and ring oscillators have already been reported. Here we show that such an approach can realize much larger scales of integration (in the present case, up to 864 transistors per circuit) and operation speeds of approximately 1 kHz in clocked sequential complementary circuits.     

A new route of fabricating porous polyimide membranes

A novel experimental route to fabricate porous polyimide membranes (PPMs) with ideal air permeability was reported. The polymer solution layer consisting of the corresponding polyamic acid (PAA), solvent, and dibutyl phthalate (DBP) with a boiling temperature of 340℃ was treated by a simple process. The polymer solution layer was first treated at a lower temperature (about 150℃), then the received solid membrane was further imidized at a higher temperature (about 270℃), and finally, DBP was removed from the membrane at a temperature above its boiling temperature. The final asymmetric polyimide membrane with a dense skin layer was obtained. To improve the air permeability of the polyimide membranes, the polymer solution layer was treated between two substrates. And the PPMs with open pores on both sides are fabricated and the air permeability of the films is improved greatly.     

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.     

高效能半导体器件进展与展望

随着数字时代的不断发展,中国"3060碳战略"目标的确立,绿色低碳成为我国各行业发展主要导向,其中,高效能半导体器件发展应用成为推动汽车电子、电子信息、大数据中心等领域节能降耗的重要趋势.从硅、锗为代表的传统半导体材料到现在以氮化镓、碳化硅为代表的第三代半导体材料,再到以金刚石、氧化镓为代表的超宽禁带半导体材料,支撑半导体器件的性能不断提升,促进射频通信、高功率器件、照明器件等方面革新发展.主要介绍了宽禁带半导体和超宽禁带半导体的研究进展,分析了高效能半导体在射频通讯、汽车电子、航空航天、新型显示等新兴领域的应用前景,总结了目前超宽禁带半导体发展主要面临的难点问题,结合当前相关的研究成果,展望高效能半导体科研、技术及产业的发展趋势,对于我国半导体科技与产业发展都具有重要的指导意义.     

Fe掺杂TiO2结构和磁性

在退火温度为773K、Fe掺杂量为n(Fe)/n(Fe+Ti)=1∶25的制备条件下,用溶胶-凝胶法在空气氛围中制备Fe掺杂TiO2稀磁半导体纳米粉末;用直流磁控溅射方法并在真空和空气氛围中结合原位退火工艺,在普通玻璃基片上制备Fe掺杂TiO2薄膜.利用X射线衍射仪(XRD)对其结构进行表征,振动样品磁强计(VSM)对磁性进行表征.结果表明,溶胶-凝胶法制备的粉末材料的磁性为室温顺磁性;直流磁控溅射法制备的薄膜样品在空气和真空氛围中均为室温铁磁性,其中真空退火能够产生更强的铁磁性.这说明可能是薄膜和基底的相互作用产生和铁磁性至关重要的氧空位,而真空环境退火能够增加氧空位.     

Preparation and characterization of cobalt-doped iron pyrite(FeS_2) thin films

Iron pyrite (FeS_2) incorporated with cobalt dopant varying from 2%to 6%atomic ratio,was synthesized by using an aqueous hydrothermal process.The thin films of Co-doped FeS_2were fabricated by a vacuum thermal evaporation of synthesized FeS_2powder.The structural,electrical and optical properties of as-deposited and sulfurized films were investigated.The X-ray diffraction results indicated that the synthesized powder and thin films showed a cubic pyrite structure.The crystallinity of FeS_2was slightly degraded by the doping of cobalt.The dependence of thin-film resistance on the temperature indicated an increase of activation energy until 3 at%cobalt doping and then decreased the resistance with the increase of cobalt concentration.Hall effect measurements showed that the Co-doped samples have n-type conduction except for the 2 at%.The carrier concentration was in the order of 10~(18)cm~(-3),whereas,the carrier mobility decreased from 6.52 cm~2/V.s to 4.3 cm~2/V.s with the increase of cobalt dopant.The photosensitivity of undoped and cobalt-doped FeS_2films was measured under AM 1.5G and NIR light.The sulfurized films showed a higher photoresponse than the asdeposited films for both visible and IR lights.     

退火温度对ZnO薄膜晶体管电特性的影响

针对非晶硅和有机薄膜晶体管的低迁移率问题,以高纯Zn为靶材,反应磁控溅射沉积、且在不同温度下退火的ZnO薄膜作为半导体活性层,成功地制备出基于ZnO材料的薄膜晶体管(ZnO-TFT),研究了退火温度对ZnO -TFT电特性的影响.结果表明:ZnO- TFT的载流子迁移率随退火温度的升高而明显增大,700℃退火的样品迁移...