| FPGA设计中的时序收敛与时钟切换 |
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| 引用本文： | 梅建超.FPGA设计中的时序收敛与时钟切换[J].科技信息,2011(1):I0127-I0129. |
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| 作者姓名： | 梅建超 |
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| 作者单位： | 中国电子科技集团公司第四十一研究所,安徽合肥233006 |
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| 摘 要： | FPGA作为最为广泛使用的可编程器件,已经广泛存在于我们的数字电路设计工作中。但是如果对FPGA缺乏深入了解,将严重影响FPGA实际工作的可靠性。本文介绍了FPGA设计中需要着重考虑的两个问题及解决方法。
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| 关 键 词： | FPGA 时序 时钟 收敛 |
Sequence Convergence and Clock Switching in FPGA Disigning |
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| MEI Jian-chao.Sequence Convergence and Clock Switching in FPGA Disigning[J].Science,2011(1):I0127-I0129. |
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| Authors: | MEI Jian-chao |
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| Institution: | MEI Jian--chao (The 41st Institute of CETC, Bengbu Anhui, 233006) |
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| Abstract: | Being a most widely used programmable component ,FPGA is widely used in our daily working while it is referred to digit circuit designing.But FPGA will be working in a unreliable condition ,if we do not know incide it very well. This papeKey words： FPGA Sequence Clock Convergencer introduces some ways to solve two FPGA-Designing questions which we must treat seriously. |
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| Keywords: | FPGA Sequence Clock Convergencer |
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