基于FPGA 的并行数码管显示控制设计

论述了采用Verilog HDL设计语言开发串行输入的多组多位数码管显示的设计思想.在硬件物理层实现串行数据的接收和硬件编码,而该物理层是采用VerilogHDL编程在FPGA上实现.利用FPGA硬件执行的并行性解决传统设计方法中难以克服的多组多位数码管显示抖动问题,这也是一种充分利用FPGA资源换取系统性能的设计方法,也易于实现数码管显示的扩展.本设计方案的VerilogHDL源代码已经完成综合并通过了布局布线后的时序仿真,系统性能完全满足实际需求.

Design of FPGA-based Parallel Digital Diode Display Control

What is introduced in the article is a line of thought about many groups and bits digital diode display control design in Verilog HDL. Both serial data received and hardware encode are realized in hardware physical layer which is performed on FPGA in Verilog HDL. By utilizing parallel capability on FPGA hardware,the Jitter on many groups and bits digital diode display is eliminated in traditional design method and this is also a design way to make the best of FPGA hardware resource to achieve better system performace. And extension of digital diode display comes true conveniently. VerilogHDL resource codes about this design project have been synthesized and completed timing simulation after fitting and routing successfully. And its performance is found to meet application requirement completely.