一种并行硬件ECC模型及FPGA实现

针对大容量固态存储器中数据错“位”的问题，目前大多采用软件ECC模型进行检错和纠错，但这势必会极大地影响存储系统的读写性能。本文基于ECC校验原理，提出一种并行硬件ECC模型，并采用FPGA实现。仿真分析和实验结果表明：该模型不仅具有良好的纠错能力，而且显著地提高了存储系统的读写性能。

A Parallel Hardware ECC Model and Its Realization with FPGA

In order to solve the problem of large-capacity solid-state memory’s wrong data bit,software ECC model is often adopted,however,it is bound to greatly affect the performance of the storage system.Based on the ECC principle,a parallel hardware ECC model is proposed,which is realized with FPGA.Simulation and experimental results show that the proposed model not only has a good error-correcting capability,but also significantly improves the reading and writing performance of the storage system.