基于FPGA的高速大容量固态存储设备数据ECC的设计与实现

针对目前高速大容量固态存储设备中,影响数据存储可靠性的错"位"问题,设计和实现了一种基于FPGA的专用ECC (Error correction code)纠错方法.在读、写操作时分别对存储数据的行和列生成校验码,通过比较两次操作的校验码,对错"位"进行精确定位和纠错,纠错能力为1 bit/512 B.相比传统纠错算法,ECC纠错方法电路实现简洁,纠错能力强,易于硬件实现.实际运行结果表明,设计完全满足高速数据记录的需求,为大容量数据存储器的可靠性提供了重要保障.

Design and Implementation of the Data ECC in High Speed and Large Capacity Solid State Storage System Based on FPGA

Solid state recorder (SSR) is currently regarded as the most reliable form of data storage medium, but within its life time, single bit error may develop with SSR. To solve this problem, this paper designs a dedicated error correction method for high-speed and large-capacity solid state storage system based on FPGA. Through comparing the ECC stored in the flash block during the write operation with the ECC calculated by the current read operation, an ECC error is detected and the data is corrected with a correcting capability up to 1bit/512B. Simple electrical system and strong correcting capability are achieved by using this method. Experimental results show that the design completely fulfils the need of high-speed data recording and ensure the reliability of the large-capacity SSR.