一种用于FPGA的单粒子翻转试验系统设计研究

单粒子翻转(SEU)试验是测试FPGA芯片抗单粒子翻转性能的重要方法.提出了一种用于测试FPGA芯片抗单粒子翻转性能的试验系统;该系统通过比对待测FPGA芯片输出数据序列和正确数据来判断是否发生数据翻转.如果发生数据翻转,则进一步统计翻转次数和翻转性质,从而能够较全面的测试FPGA芯片的抗单粒子翻转性能.运用该试验系统对某款FPGA芯片进行了单粒子翻转试验,测试结果显示该试验系统能够正确评估被测芯片的抗单粒子翻转性能.

Design and Research of single event upset test system for FPGA

Single Event Upset (SEU) test is an important way to test anti-SEU performance of FPGA chip. This paper proposes a test system for testing anti-SEU performance. The system determine whether a data flips by comparing the sequence of output data and the correct data .If the data inversion occurs, the number of inversion and the nature of flip are counted. Hence, it enables a more comprehensive test for the anti-SEU performance of FPGA chip. We conduct the anti-SEU test using the test system mentioned in this paper, the test results show that the test system is able to correctly assess the anti-SEU performance of the FPGA chip.