基于FPGA的模数混合编帧的采集系统

介绍了一种以FPGA为核心逻辑控制模块的数据采集系统的设计。设计中采用了16位的AD8405作为模数转换器,FPGA作为中心逻辑控制模块,对弹上的不同速率的模拟信号与接收的数字信号进行采集,并将采集的信号通过数据帧格式的形式混合编帧和存储,再通过串口完成与上位机的通信。FPGA模块采用VHDL语言进行设计。该系统在测试状态下通过地面测试系统对该采编器的采集过程进行实时监测,并对其功能进行检测。

Acquisition system of mixed coding frame of analog-to-digital data based on FPGA

The design of the multi-channel sampling encoder based on FPGA, which is the core logic control module of the system is introduced. The design uses a 16-bit AD8405 as the ADC. FPGA as a central logic control module, it completes data acquisition on the different rate of the analog signal and the received digital signal, and acquisition of signals in data frame format in the form of mixed frame and storage, communicating with host computer via the serial interface. FPGA modules uses VHDL dialogue .This system uses ground test system for real-time monitoring and feature detection to the acquisition process of the editors in a test state.