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基于坐标逻辑的形态图像处理器的硬件实现
引用本文:张波,张焕春,经亚枝.基于坐标逻辑的形态图像处理器的硬件实现[J].华中科技大学学报(自然科学版),2004,32(6):52-54.
作者姓名:张波  张焕春  经亚枝
作者单位:南京航空航天大学,自动化学院,江苏,南京,210016;南京航空航天大学,自动化学院,江苏,南京,210016;南京航空航天大学,自动化学院,江苏,南京,210016
摘    要:在阐述坐标逻辑运算的基础上,论述了基于坐标逻辑形态学硬件实现的图像处理系统,该系统采用DSP FPGA的框架结构,利用FPGA的可重构特性将其中一片FPGA作为协处理器可以实现不同的图像处理功能,将坐标逻辑和传统形态学硬件实现的形态图像处理器在处理效果和速度两个方面作了比较,算法在FPGA芯片上的高速实现特征使数学形态学在图像实时处理领域的应用成为可能。

关 键 词:图像处理器  坐标逻辑  可重构  协处理器  DSP  FPGA
文章编号:1671-4512(2004)06-0052-03
修稿时间:2003年9月16日

A hardware realization of morphological image processor based on coordinate logic
Zhang Bo Zhang Huanchun Jing YazhiZhang Bo Dr., College of Automation Eng.,Nanjing Univ. of Aeronautics & Astronautics,Nanjing ,China..A hardware realization of morphological image processor based on coordinate logic[J].JOURNAL OF HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY.NATURE SCIENCE,2004,32(6):52-54.
Authors:Zhang Bo Zhang Huanchun Jing YazhiZhang Bo Dr  College of Automation Eng  Nanjing Univ of Aeronautics & Astronautics  Nanjing  China
Institution:Zhang Bo Zhang Huanchun Jing YazhiZhang Bo Dr., College of Automation Eng.,Nanjing Univ. of Aeronautics & Astronautics,Nanjing 210016,China.
Abstract:The basis of a coordinate logic operations (CLO) was introduced and an image processing system with coordinate logic implemented by hardware presented. The system was composed of DSP and FPGA.One FPGA as coprocessor may implement different functions due to its re-configurable characteristic. The image processors realized by coordinate logic and standard morphology were compared in effect and speed. The algorithm was implemented and its speed was very high. It makes possible that mathematical morphology is applicable in real time image processing.
Keywords:image processor  coordinate logic  re-configurable  coprocessor  DSP  FPGA
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