PDH标准的E3次群测试序列发生器的FPGA设计

为了提高PDH标准下E3次群信号通信设备的可靠性及功能的多样性,设计了一种基于FPGA器件的测试序列发生器系统。在整个设计过程中,完成了测试系统各个功能模块的设计与硬件实现,其中主要包括系统控制模块、PRBS生成模块、误码生成模块和HDB3码转换模块。利用Quartus II软件内嵌的Signal Tap II Logic Analyzer对序列发生器进行了实时的测试,结果比较准确,能够完成测试所需的基本工作任务,因此该测试系统的设计具有一定的实用价值。

Test Sequence Generator of E3 Group with PDH Standard Designed by FPGA

In order to improve the reliability and the diversity of function of E 3 group signal communication equipment with PDH standard, we designed a test sequence generator system based on FPGA device .In the whole process of design , we completed the implementation of hardware and the design of each function module of test system , which mainly included the system control mod-ule , PRBS generation module , error code generation module and HDB 3 code conversion module .Using SignalTap II Logic Analy-zer module embedded in Quartus II software for real -time testing of the sequence generator , the result is more accurate .The se-quence generator can complete the basic tasks required to test , so it has certain practical value to design the test system .