| 基于SVA的FPGA接口时序验证方法研究 |
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| 引用本文： | 颜丽,王伟,黄莉雅.基于SVA的FPGA接口时序验证方法研究[J].萍乡高等专科学校学报,2014,31(3):50-54. |
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| 作者姓名： | 颜丽 王伟 黄莉雅 |
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| 作者单位： | 1. 萍乡学院,江西萍乡,337000
2. 九江职业技术学院,江西九江,332007 |
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| 摘 要： | 本文介绍一种基于SVA(System Verilog Assertion)的FPGA接口时序验证实现方法,此方法以FPGA接口下级芯片的手册为基础,将手册中接口时序条件转换成SVA断言,并且在验证运行过程中,自动监测接口信号时序以到自动验证FPGA接口时序的目的。
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| 关 键 词： | FPGA 接口时序 SVA |
A Timing Verification Method of FPGA Interface Based on SVA |
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| Yan Li,Wang Wei,Huang Liya.A Timing Verification Method of FPGA Interface Based on SVA[J].Journal of Pingxiang College,2014,31(3):50-54. |
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| Authors: | Yan Li Wang Wei Huang Liya |
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| Institution: | Yan Li, Wang Wei, Huang Liya (1. PingXiang University, Pingxiang, Jiangxi 337000; 2. JiuJiang Vocational and Technical College, JiuJiang, Jiangxi 332007) |
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| Abstract: | The paper gives an introduction to a timing verification method of FPGA interface based on SVA（System Verilog Assertion）. This method is based on the sheet of chip connected to the FPGA interface, and changing the timing conditions of interfaces in the sheet to SVA code. In the process of verification, interface signal is monitored automatically, and timing of FPGA interface is verified automatically. |
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| Keywords: | FPGA interface timing SVA |
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