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基于FPGA的数字误码测试系统设计与实现
引用本文:唐庭龙,夏平,刘馨琼.基于FPGA的数字误码测试系统设计与实现[J].三峡大学学报(自然科学版),2009,31(3):80-82,112.
作者姓名:唐庭龙  夏平  刘馨琼
作者单位:1. 三峡大学电气信息学院,湖北,宜昌,443002
2. 三峡大学电气信息学院,湖北,宜昌,443002;三峡大学智能视觉与图像信息研究所,湖北,宜昌,443002
基金项目:湖北省教育厅自然科研基金项目 
摘    要:设计了逐位比较型数字通信误码测试系统.首先,分析了误码测试系统的基本架构及其各组成功能模块;其次,讨论了误码测试系统中各关键模块的实现方法;最后,利用QuartusII7.2软件平台对设计的数字误码测试系统进行了仿真分析,验证了设计的正确性.

关 键 词:误码测试系统  FPGA  位同步  m序列

Design and Implementation of BER Test System Based on FPGA
Tang Tinglong,Xia Ping,Liu Xinqiong.Design and Implementation of BER Test System Based on FPGA[J].Journal of China Three Gorges University(Natural Sciences),2009,31(3):80-82,112.
Authors:Tang Tinglong  Xia Ping  Liu Xinqiong
Institution:Tang Tinglong Xia Ping Liu Xinqiong (1. College of Electrical Engineering & Information Science, China Three Gorges Univ. , Yichang 443002, China; 2. Institute of Intelligent Vision & Image Information, China Three Gorges Univ. , Yichang 443002, China)
Abstract:ehiteeture mentation tus II 7.2 Digital communications BER test system based on bit comparison is designed. Firstly, the basic ar of the BER test system and its constituent functional modules are analyzed. Secondly, the imple methods of the key device module are discussed. Finally, the system is utilized to simulate in Quar design software platform; and the correctness of its design is verified.
Keywords:FPGA
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