| 一种10bit 50MS/s低功耗流水线模数转换器 |
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| 引用本文： | 周文君,张科,李文宏.一种10bit 50MS/s低功耗流水线模数转换器[J].复旦学报(自然科学版),2011(4):450-456. |
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| 作者姓名： | 周文君 张科 李文宏 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室; |
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| 基金项目： | 国家高技术研究发展计划(“863”计划)(2009AA011607)资助项目 |
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| 摘 要： | 设计了一个10 bit精度,50 MS/s采样频率的流水线型模数转换器,通过运算放大器共享和省略采样保持实现低功耗.第1级为单比特输出,它能够在将信号摆幅减半的同时保持信噪比不衰减,减半的摆幅使得运放直流增益和带宽要求以及电容匹配要求降低.由于采用运放共享技术,该设计只使用了4个运放,功耗相比传统结构降低1/3.采用0...
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| 关 键 词： | 模数转换器 流水线 低功耗 运放共享 无采样保持 |
A Low Power 10-bit 50-MS/s Pipelined A/D Converter |
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| ZHOU Wen-jun,ZHANG Ke,LI Wen-hong.A Low Power 10-bit 50-MS/s Pipelined A/D Converter[J].Journal of Fudan University(Natural Science),2011(4):450-456. |
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| Authors: | ZHOU Wen-jun ZHANG Ke LI Wen-hong |
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| Institution: | ZHOU Wen-jun,ZHANG Ke,LI Wen-hong(State Key Laboratory of ASIC and systems,Fudan University,Shanghai 201203,China) |
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| Abstract: | With SHA-less architecture and op amp-sharing technique,a low power 10bit 50MS/s pipelined analog-to-digital convertor(ADC) is proposed in this paper.The first stage with 1-bit-per-stage architecture achieves half signal swing while SNR still remains the same.The reduction of the signal swing allows relatively lower DC gain and bandwidth of op amp;it also relaxes the requirement of capacitor matching.Only four op amps are used in the design due to the opamp-sharing technique,resulting in more than 1/3 reduc... |
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| Keywords: | analog-to-digital converter pipelined low power op amp-sharing SHA-less |
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