基于原模图LDPC码的联合信源信道译码器的硬件实现

采用FPGA(field programmable gate array)设计基于原模图低密度奇偶校验(low density parity check,LDPC)码的联合信源信道译码器,信道部分和信源部分都是由原模图LDPC码组成.在原模图LDPC码联合译码器的硬件实现架构中,通过2步循环扩展得到了适合硬件实现的准循环原模图LDPC码,译码器信息的迭代更新采用TDMP (Turbo decoding message passing)分层译码算法,采用的归一化最小和算法使得P-JSCD(photograph-based joint source and channel decoding)具有部分并行结构.最后,为了降低资源消耗和译码延迟,采用了提前终止迭代策略.基于FPGA平台的硬件实现结果表明,该联合译码器的译码性能非常接近相应的浮点算法,并且最大时钟频率达到193.834 MHz,吞吐量为24.44 Mbit/s.

Hardware implementation of a joint source-channel decoder based on photograph LDPC codes

Photograph-based joint source and channel decoding (P-JSCD), where both source code and channel code are composed of photograph low density parity check(LDPC) codes,exhibit a significant BER performance improvement.In this paper, we present a hardware implementation architecture for P-JSCD. In the proposed hardware implementation architecture, the easy-hardware-implementation quasi cyclic photograph-based LDPC code is obtained by utilizing a two-step lifting procedure. Due to the use of the normalized Min-Sum algorithm based on the Turbo decoding message passing (TDMP) layered decoding scheme, the proposed P-JSCD has a partially paralleling architecture. Furthermore, an early termination strategy is introduced to reduce the power consumption and decoding latency. The proposed P-JSCD is evaluated on a Xilinx Spartan 6 FPGA (Field programmable gate array) platform and the results indicate that the maximum frequency is 193.834 MHz, corresponding to 24.44Mbps of the decoding throughput.