利用循环计数器优化设计实现卷积交织器

卷积交织器和去卷积交织器的实现方法有多种,本文基于Altera公司开发的Max PlusII软件平台和仿真环境,以DVB-C系统中深度I=12的卷积交织为例,利用循环计数器设计实现先进先出(FIFO)移位存储器,提出了一种使用理论最小资源的方法来实现卷积交织器,最高工作频率可以达到80MHz,而不使用片外RAM,仅使用Altera的FLEX10KE系列器件中的EAB.

Using Cycle-Counter's Optimization Design To Realize Convolutional Interleaver

We often realize FIFO in digital system by shift register.The data in the register shift to the next register with the clock.We can use the pointer idea in computer,change the shift of data to the shift of pointer.After that we can save the source by storing the data together.The EAB in Altera' s FLEX,APEX,and Cyclone series device can realize the block storage. This paper bases on the Altera company's Max+PlusII Software and simulation environment,takes the Convolutional Interleaver with deep I=12 in the DVB-C system as an example,proposes a method to realize Convolutional Interleaver with theoretical minimum resource consumption.The highest working frequence can reach 80MHz.In this design,we realize Convolutional Interleaver without the RAM which is out of the chip.we only use the EAB in the Altera's FLEX10KE series devices because of the using of pointer idea.