| 基于FPGA的神经网络硬件实现方法 |
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| 引用本文： | 李昂,王沁,李占才,万勇.基于FPGA的神经网络硬件实现方法[J].北京科技大学学报,2007,29(1):90-95. |
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| 作者姓名： | 李昂 王沁 李占才 万勇 |
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| 作者单位： | 北京科技大学信息工程学院,北京,100083 |
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| 摘 要： | 提出了一种可以灵活适应不同的工程应用中神经网络在规模、拓扑结构、传递函数和学习算法上的变化,并能及时根据市场需求快速建立原型的神经网络硬件可重构实现方法.对神经网络的可重构特征进行了分析,提出了三种主要的可重构单元;研究了可重构的脉动体系结构及BP网络到该结构映射算法;探讨了具体实现的相关问题.结果表明,这种方法不仅灵活性强,其实现的硬件也有较高的性价比,使用一片FPGA中的22个乘法器工作于100 MHz时,学习速度可达432 MCUPS.
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| 关 键 词： | 神经网络 FPGA 可重构 脉动阵列 FPGA 神经网络 硬件实现 方法 based hardware implementation networks 学习速度 工作 乘法器 使用 性价比 活性 结果 问题 相关 映射算法 体系结构 脉动 可重构单元 |
| 修稿时间： | 2005-11-09 |
Neural networks hardware implementation based on FPGA |
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| LI Ang,WANG Qin,LI Zhancai,WAN Yong.Neural networks hardware implementation based on FPGA[J].Journal of University of Science and Technology Beijing,2007,29(1):90-95. |
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| Authors: | LI Ang WANG Qin LI Zhancai WAN Yong |
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| Institution: | Information Engineering School, University of Science and Technology Beijing, Beijing 100083, China |
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| Abstract: | For different engineering applications, neural networks varied in scale, topology, transfer functions and learning algorithms. A reconfigurable approach for neural hardware implementation was proposed, which was not only flexible to meet those changes, also with the fast prototyping ability for market requirements. Three kinds of reconfigurable processing units were presented based on the analysis of neural network's reconfiguration. A reconfigurable systolic architecture was put forward and the method of mapping BP networks into this architecture was introduced. Implementation issues were discussed with an example. The results showed that a high learning speed of 432?M CUPS(Connections Updated Per Second)was achieved (working at 100?MHz using 22 multipliers) at a reasonable cost. |
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| Keywords: | neural networks FPGA reconfigurable systolic |
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