| JPEG 2000自适应算术编码器FPGA设计 |
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| 引用本文： | 杨珂,刘明业.JPEG 2000自适应算术编码器FPGA设计[J].北京理工大学学报,2005,25(3):234-238. |
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| 作者姓名： | 杨珂 刘明业 |
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| 作者单位： | 北京理工大学,信息科学技术学院计算机科学工程系,北京,100081;北京理工大学,信息科学技术学院计算机科学工程系,北京,100081 |
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| 摘 要： | 研究JPEG 2000标准中自适应算术编码器的硬件实现问题, 提出一种适合ASIC实现的并行结构, 并在FPGA上对其进行了仿真验证.该设计使用VHDL语言在RTL级描述; 并以XILINX XC2V8000-5FF1152为基础, 在ISE 5.2下完成综合及后仿真.在整个JPEG 2000设计中, 最高工作时钟66 MHz, 自适应算术编码器处理速度可达到0.25 bit/cycle.
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| 关 键 词： | JPEG 2000 嵌入式块编码 算术编码器 FPGA 图像压缩 硬件描述语言 |
| 文章编号： | 1001-0645(2005)03-0234-05 |
| 收稿时间： | 2004/5/10 0:00:00 |
| 修稿时间： | 2004年5月10日 |
FPGA Design of Adaptive Arithmetic Encoder for JPEG 2000 |
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| YANG Ke and LIU Ming-ye.FPGA Design of Adaptive Arithmetic Encoder for JPEG 2000[J].Journal of Beijing Institute of Technology(Natural Science Edition),2005,25(3):234-238. |
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| Authors: | YANG Ke and LIU Ming-ye |
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| Institution: | Department of Computer Science and Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing100081, China;Department of Computer Science and Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing100081, China |
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| Abstract: | FPGA implementation of the adaptive arithmetic encoder in JPEG2000 standard is investigated. A parallel architecture suitable for ASIC implementation is presented, which is simulated and verified on FPGA.The design is described with VHDL at RT level. Based on XILINX XC2V8000-5FF1152, synthesis and postsimulation are conducted with ISE 5.2. The JPEG 2000 encoder system works at 66 MHz, it costs the adaptive arithmetic encoder about 1 cycle to encode 0.25 bit. |
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| Keywords: | JPEG 2000 EBCOT arithmetic encoder FPGA image compression VHDL |
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