| FFT的ASIC实现及FPGA验证 |
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| 引用本文： | 赵 莹`,李 云,刘解华,马文勃.FFT的ASIC实现及FPGA验证[J].科学技术与工程,2015,15(4). |
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| 作者姓名： | 赵 莹` 李 云 刘解华 马文勃 |
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| 作者单位： | 重庆邮电大学 信息产业部移动通信重点实验室,重庆邮电大学 信息产业部移动通信重点实验室,北京华力创通科技股份有限公司,北京华力创通科技股份有限公司 |
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| 基金项目： | 国家高技术研究发展计划(863计划)资助,课题编号2012AA01A508, 国家科技重大专项课题(2013ZX03006003-002)。 |
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| 摘 要： | 通过对FFT(fast fourier transformation),即快速傅里叶变换的一般算法的研究对比,确定合理可行的基2方法处理1024点FFT。在ASIC(application specific integrated circuit)专用集成电路上实现FFT硬件模块,并将该模块在FPGA(Field Programmable Gate Array)上进行原型验证。本文采用级联结构设计FFT模块,在尽量减小资源消耗的同时,提高FFT的运算速度。设计采用两组四个深度为256的双口RAM,乒乓结构处理,完成整个运算仅用了1320个周期。最后用Xilinx公司的Vertex7-XC7VX690T芯片做FPGA原型验证,在时钟频率为50MHz时,完成1024点FFT仅用了26.2us。
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| 关 键 词： | 关 键 词：FFT FPGA ASIC 双口RAM 乒乓结构 |
| 收稿时间： | 2014/9/23 0:00:00 |
| 修稿时间： | 2015/1/14 0:00:00 |
FFT implementation base on ASIC and verification based on FPGA |
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| Zhao Ying,Li Yun,Liu Jie Hua and Ma Wen Bo.FFT implementation base on ASIC and verification based on FPGA[J].Science Technology and Engineering,2015,15(4). |
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| Authors: | Zhao Ying Li Yun Liu Jie Hua and Ma Wen Bo |
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| Institution: | Chongqing University of posts and telecommunications,Hwa Create Corporation Ltd,Hwa Create Corporation Ltd |
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| Abstract: | By the comparison of different FFT algorithms, a reasonable and feasible radix-2 algorithm is designed to deal with the 1024 points FFT. The designed algorithm is implemented with a ASIC module and tested on PFGA verification platform. Compared with many hardware implementation structures, the cascade structure is chosen to implement the FFT hardware. The FFT hardware implementation reduces the resource consumption and computation overhead. Here a ping-pang architecture with 2 groups of four RAM, which the depth is 256 and two port , is used to complete 1024 point FFT only in 1320 cycles. Finally, the FPGA simulation is conducted in the Xilinx Vertex7-XC7VX690T chip. Under 50MHz time frequency 1024 points FFT is completed only in 26.2us. |
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| Keywords: | FFT FPGA ASIC dual port RAM ping-pang architecture |
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