| PCI总线接口控制器的FPGA设计 |
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| 引用本文： | 王友波,刘明业.PCI总线接口控制器的FPGA设计[J].北京理工大学学报,2004,24(5):423-426. |
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| 作者姓名： | 王友波 刘明业 |
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| 作者单位： | 北京理工大学,信息科学技术学院计算机科学工程系,北京,100081 |
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| 基金项目： | 国家重点基础研究发展计划(973计划) |
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| 摘 要： | 研究有限状态机与PCI总线接口控制器的设计问题.在分析PCI总线接口控制器基本功能的基础上,给出其顶层设计.根据PCI总线操作时序,提出了从设备接口控制器的有限状态机模型.同时结合Altera FLEX10K的FPGA器件,采用Verilog硬件描述语言,描述该总线控制器的基本操作,并完成功能仿真与综合,实现了PCI总线控制器的FPGA设计,说明该有限状态机具有结构清晰、易于维护的特点.
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| 关 键 词： | PCI总线接口 有限状态机 FPGA设计 总线接口控制器 FPGA 顶层设计 Controller Interface PCI Bus 维护 结构 综合 功能仿真 基本操作 总线控制器 描述语言 硬件 Verilog 器件 Altera 结合 有限状态机模型 设备 |
| 文章编号： | 1001-0645(2004)05-0423-04 |
| 收稿时间： | 1/4/2004 12:00:00 AM |
| 修稿时间： | 2004年1月4日 |
FPGA Design of PCI Bus Interface Controller |
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| WANG You-bo and LIU Ming-ye.FPGA Design of PCI Bus Interface Controller[J].Journal of Beijing Institute of Technology(Natural Science Edition),2004,24(5):423-426. |
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| Authors: | WANG You-bo and LIU Ming-ye |
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| Institution: | Department of Computer Science and Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing100081, China;Department of Computer Science and Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing100081, China |
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| Abstract: | Studies issues in the finite state machine (FSM) design in PCI bus interface controllers. The PCI top-level block design is first presented in terms of the bus interface controller. The FSM model of target PCI bus interface controller is then provided based on PCI bus operation timing. The basic operation of the bus controller is described with the Altera's FLEX10K FPGA device and Verilog HDL, along with the function simulation and synthesis and the FPGA design of the PCI bus controller. This brings out the strong points of the FSM, such as its clear structure and easy maintance. |
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| Keywords: | PCI bus interface finite state machine FPGA design |
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