| 重模多项式乘法在FPGA上的实现 |
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| 引用本文： | 胡波,赵红芳,冯春雨,王怀瑞.重模多项式乘法在FPGA上的实现[J].东南大学学报(自然科学版),2010,40(Z2). |
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| 作者姓名： | 胡波 赵红芳 冯春雨 王怀瑞 |
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| 作者单位： | 河北省科学院应用数学研究所;河北省数学研究中心;河北省科学院;石家庄开发区冀科双实科技有限公司; |
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| 基金项目： | 河北省自然科学基金数学研究专项资助项目 |
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| 摘 要： | 为降低基于重模多项式剩余类环矩阵的密码算法中乘法运算占用的硬件资源量,提出了一种剩余类环上乘法的流水线实现方法.该方法选用数模为216,多项武模为4次首一多项式的重模多项式剩余类环,对流水线设计进行了数学推导,给出了重模多项式剩余类环上可综合乘法模块和不可综合测试模块的Verilog HDL代码,并利用ModelSim软件进行仿真测试.测试结果表明,此方法不仅能够提高乘法运算的速度,而且将16位乘法器的数目从28个降到8个,大大降低了硬件资源消耗量,使得重模多项式剩余类环上矩阵乘法在一般的硬件电路中得以实现,为该类密码算法的推广和应用奠定了基础.
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| 关 键 词： | 重模多项式剩余类环 FPGA 集成电路 |
Implementation of double-module polynomial multiplication on FPGA |
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| Hu Bo,Zhao Hongfang,Feng Chunyu,Wang Huairui.Implementation of double-module polynomial multiplication on FPGA[J].Journal of Southeast University(Natural Science Edition),2010,40(Z2). |
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| Authors: | Hu Bo Zhao Hongfang Feng Chunyu Wang Huairui |
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| Institution: | Hu Bo1,2 Zhao Hongfang3 Feng Chunyu4 Wang Huairui1(1Institute of Applied Mathematics,Hebei Academy of Sciences,Shijiazhuang 050081,China)(2 Hebei Mathematics Research Center,China)(3 Hebei Academy of Sciences,China)(4SJZ JKSS Technology Co.,Ltd,China) |
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| Abstract: | To reduce the hardware consumption,a pipe-line method is proposed to implement the multiplication in double-module polynomial residue ring.The method chooses 216 as integer module and any quartic polynomial with the leading coefficient to be one as polynomial module.The pipe-line method is designed according to mathematical derivation.The synthesizable multiplication module and the test module which is unsynthesizable are compiled by Verilog HDL.Finally,the pipe-line method is simulated on ModelSim.The test... |
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| Keywords: | double-module polynomial residue class ring field programmable gate array(FPGA) integrated circuit |
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