| 基于CPLD的高速采集系统设计 |
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| 引用本文： | 于长胜,周永勤.基于CPLD的高速采集系统设计[J].应用科技,2006,33(4):13-15. |
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| 作者姓名： | 于长胜 周永勤 |
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| 作者单位： | 哈尔滨理工大学,电气与电子工程学院,黑龙江,哈尔滨,150040 |
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| 摘 要： | 采用高速A/D转换器和CPLD设计出了高速数据采集系统，利用多字节写入、单字节读出的方法降低数据写入的相对速度，实现了高速、大容量连续采样数据的存储．该系统既降低了生产成本及设计的复杂程度，又不失灵活性和实时性，是一种比较合理的高速数据采集方案．
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| 关 键 词： | 高速数据采样 可编程逻辑器件 快速存储 |
| 文章编号： | 1009-670X（2006）04-0013-03 |
| 收稿时间： | 2005-11-21 |
| 修稿时间： | 2005年11月21 |
Design of high-speed sampling system based on CPLD |
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| YU Chang-sheng,ZHOU Yong-qin.Design of high-speed sampling system based on CPLD[J].Applied Science and Technology,2006,33(4):13-15. |
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| Authors: | YU Chang-sheng ZHOU Yong-qin |
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| Abstract: | Data collection is an important part of an electronic measurement and control system. The system of high-speed data sampling is designed with high-speed ADC and CPLD in this paper. The system adopts multibyte writing and single-byte reading method to slow down the relative speed of data writing so that the storage is achieved for high-speed, large volume continuous sampled data. The system reduces the cost and complexity of the design, as well as remains its flexibility and real-time property. |
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| Keywords: | high-speed data collection CPLD DMA |
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