首页 | 本学科首页   官方微博 | 高级检索  
     检索      

叶端定时传感器脉冲信号高速采集系统的FPGA实现
引用本文:谢海鸿,王宇华,李萍.叶端定时传感器脉冲信号高速采集系统的FPGA实现[J].四川理工学院学报(自然科学版),2006,19(3):93-96.
作者姓名:谢海鸿  王宇华  李萍
作者单位:佛山科学技术学院机电与信息工程学院,广东,佛山,528000
摘    要:在非接触式高速旋转叶片自动实时监测系统中,要求25μm的振动位移测量分辨率,为采集电路的设计增加了很大的难度。由于信号处理系统用固定频率脉冲填充法计数,实现定时时间的测量。因此采集系统的设计关键问题是:计数器频率达100MHz的24bit高速计数器的设计和利用D触发器使锁存脉冲与100MHz的计数时钟同步,从而解决由于计数脉冲与锁存脉冲不同步所造成的数据锁存失误问题。锁存器的数据由EPP接口采集到计算机中进行处理。实验证实了该系统性能良好,达到预定精度要求。

关 键 词:叶端定时传感器  数据采集  FPGA  EPP
文章编号:1673-1549(2006)03-0093-04
修稿时间:2005年11月28

Design of Tip-timing Sensor Pulse Signal High Speed Sampling System Based on FPGA
XIE Hai-hong,Wang Yu-hua,LI ping.Design of Tip-timing Sensor Pulse Signal High Speed Sampling System Based on FPGA[J].Journal of Sichuan University of Science & Engineering:Natural Science Editton,2006,19(3):93-96.
Authors:XIE Hai-hong  Wang Yu-hua  LI ping
Abstract:In the non-contact real time detection of high speed rotating blade,because of the required 25μm measurement accuracy of vibration distance,the design of data acquisition circuit is rather difficult.Fixed-frequency pluses filling method is adopted to realize the measurement of tip timing.Two key points are solved in the design,one is the realization of 24-bit high speed counter whose counting clock is 100MHz;the other is D flip-flop being used to solve synchronous of latching clock and counting clock,with the result than the error latching caused by signal be not synchronous.The data is acquired through EEP and then processed by computer.It has been proved by the experiment that the system is able to obtain the required accuracy.
Keywords:FPGA  EPP
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号