FPGA内部时钟系统间的FIFO数据接口

在现场可编程逻辑芯片的设计过程中，不同模块之间的数据接口，尤其是不同时钟系统的各个模块之间的数据接口是系统设计的一个关键．用异步FIFO模块来实现接口，接口双方都在自己时钟的同步下进行工作，它们之间不需要互相握手，只需跟接口FIFO模块进行交互就可以了，即向接口FIFO模块中写入数据或从FIFO模块中读出数据．用这样一个缓冲FIFO模块实现FPGA内部不同时钟系统之间的数据接口，使设计变得非常简单和容易．所用的FIFO接口是XILINX公司提供的IP核，经过充分测试和优化，系统运行稳定，占用的FPGA内部资源也非常少。

FIFO Data Interface Between Clock Systems Inside FPGA

The interface of the different module, especially the interface between different clock systems is key in the digital logic system design.A simple method is used for the asynchronous FIFO. In this method the interface becomes very easy and also stable,and the two sides operate inside its own clock system. There is no need to shake hand with the other clock system. They just write data into the asynchronous FIFO and read data from the asynchronous FIFO. The FIFO is one of the IP CORE offered by XILINX Corporation. It is tested carefully and occupies small resource. It's worth to use.