| 基于CPLD的多功能计时器的设计 |
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| 引用本文： | 梁丽.基于CPLD的多功能计时器的设计[J].北京工商大学学报(自然科学版),2005,23(1):53-55. |
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| 作者姓名： | 梁丽 |
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| 作者单位： | 北京工商大学,信息工程学院,北京,100037 |
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| 摘 要： | 简述了EDA技术在电子系统设计中的功能和作用,阐述了用EDA工具和可编程逻辑器件设计多功能计时器的开发流程、仿真结果.实践表明,利用EDA技术进行电子系统的设计,有着设计快速、调试方便、研制周期短、系统可靠性高等一系列的优点,EDA技术是现代电子设计的发展趋势.
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| 关 键 词： | EDA技术 可编程逻辑器件 CPLD |
| 文章编号： | 1671-1513(2005)01-0053-03 |
| 修稿时间： | 2004年9月2日 |
DESIGN OF MULTI-FUNCTION TIMER BASED ON CPLD |
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| LIANG Li.DESIGN OF MULTI-FUNCTION TIMER BASED ON CPLD[J].Journal of Beijing Technology and Business University:Natural Science Edition,2005,23(1):53-55. |
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| Authors: | LIANG Li |
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| Abstract: | Described the function and operation of EDA technique in application of the electronic system design. Allustrated the design process of multi-function timer using EDA tools and programmable logic device. Obtained the result of computer simulation. Practically showing, there were a lot of strongpoint that the design of electronic system by EDA technique. Such as design fast, debug easy, develop period short and system dependability high. EDA technique is the evolution tide of modern electronic design. |
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| Keywords: | EDA technique programmable logic device CPLD |
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