| 可配置高速二维卷积处理器设计与Gabor滤波应用 |
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| 引用本文： | 陈实,苏光大,陆建华.可配置高速二维卷积处理器设计与Gabor滤波应用[J].清华大学学报(自然科学版),2010(4). |
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| 作者姓名： | 陈实 苏光大 陆建华 |
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| 作者单位： | 清华大学电子工程系; |
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| 基金项目： | 国家自然科学基金资助项目(60672109); 国家“九七三”重点基础研究项目(2007CB310600) |
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| 摘 要： | 针对具有多种大尺寸卷积内核的Gabor滤波器组,设计了可配置二维卷积处理器来实现硬件加速。该处理器利用FPGA(field programmable gate array)内部逻辑资源构建具有多级流水线的二维卷积运算单元,并通过子块分割及重组来支持任意尺寸的卷积运算。使用高级语言对其控制器编程来实现对卷积运算单元及数据流的配置,从而实现Gabor滤波。实验表明:使用EP2C70F896C6型FPGA工作在75MHz,对于120×90像素的灰度图像计算五尺度八方向Gabor滤波(最大尺寸为41×41像素,系数为复数)总耗时28.8ms。
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| 关 键 词： | 模式识别 卷积 Gabor滤波 并行计算 FPGA |
Configurable high speed 2-D convolution processor and Gabor filter application |
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| CHENShi,SUGuangda,LUJianhua.Configurable high speed 2-D convolution processor and Gabor filter application[J].Journal of Tsinghua University(Science and Technology),2010(4). |
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| Authors: | CHENShi SUGuangda LUJianhua |
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| Institution: | CHEN+Shi,SU+Guangda,LU+Jianhua(Department+of+Electronic+Engineering,Tsinghua+University,Beijing+100084,China) |
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| Abstract: | A reconfigurable 2-D convolution processor was developed to accelerate the Gabor filter group with various large scale kernels. The processor utilizes logic resources of field programmable gate array (FPGA) to build up pipelined parallel convolution matrix,which is segmented and flexibly reorganized,thus can support any scale. The Gabor filter is implemented by using high level language to program its controller for configuration of convolution matrix and data flow. Experimental results indicate that Gabor ... |
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| Keywords: | pattern recognition convolution Gabor filter parallel computing FPGA |
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