| 基于VHDL的数字频率计的设计 |
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| 引用本文： | 马茵,王慧.基于VHDL的数字频率计的设计[J].科技信息,2011(27):I0077-I0077,I0090. |
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| 作者姓名： | 马茵 王慧 |
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| 作者单位： | 河南工业职业技术学院; |
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| 摘 要： | 本文的数字频率计设计,采用自上向下的设计方法,实现整个电路的测试信号控制、数据运算处理和控制数码管的显示输出。一块复杂可编程逻辑器件CPLD芯片EPM7128SLC84-15完成各种时序逻辑控制、计数功能。在MAX+PLUS II平台上,用VHDL语言编程完成了CPLD的软件设计、编译、调试、仿真。本文详细论述了系统自上而下的设计方法及CPLD的软件编程设计。
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| 关 键 词： | EDA技术 CPLD MAX PLUSII 频率计 |
VHDL-based Design of Digital Frequency Meter |
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| MA Yin WANG Hui.VHDL-based Design of Digital Frequency Meter[J].Science,2011(27):I0077-I0077,I0090. |
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| Authors: | MA Yin WANG Hui |
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| Institution: | MA Yin WANG Hui(Henan Polytechnic Institute,Nanyang Henan,473009,China) |
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| Abstract: | This digital frequency meter design,the use of top-down design approach,the entire circuit of the test signal control,data processing and control operations of digital display output.A complex programmable logic device CPLD chip EPM7128SLC84-15 to complete a variety of temporal logic control,counting function.In the MAX + PLUS II platform,complete with VHDL CPLD programming software design,compilation,debugging,simulation.This paper discusses in detail the system top-down design methods and software program... |
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| Keywords: | EDA technology CPLD MAX PLUS II Frequency meter |
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