| 智能高速频率计设计 |
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| 引用本文： | 李建科,曾文献,魏志军.智能高速频率计设计[J].河北省科学院学报,2006,23(2):45-48. |
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| 作者姓名： | 李建科 曾文献 魏志军 |
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| 作者单位： | 河北经贸大学,河北,石家庄,050061 |
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| 摘 要： | 论述了一种频率测量范围为1 Hz4 GHz高分辨率频率计的设计方法.智能高速频率计数器分成两个通道,利用ECL逻辑电平高速芯片和CPLD共同完成对高频信号的整形和计数,采用单片机进行智能控制和显示,具有多时基档位转换、频率测量、周期测量、自动校准、外部计数等多种功能.
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| 关 键 词： | 频率计 ECL电平 高速芯片 CPLD 单片机 |
| 文章编号： | 1001-9383(2006)02-0045-04 |
| 修稿时间： | 2006年1月23日 |
Design of intelligent high-speed cymometer |
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| LI Jian-ke,ZENG Wen-xian,WEI Zhi-jun.Design of intelligent high-speed cymometer[J].Journal of The Hebei Academy of Sciences,2006,23(2):45-48. |
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| Authors: | LI Jian-ke ZENG Wen-xian WEI Zhi-jun |
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| Abstract: | The design process of a 1Hz-4GHz frequency measuring range and high resolution cymometer is discussed.Two chanels is designed for the intelligent high-speed cymometer use,high-speed chips with ECL logic level and counter based on CPLD are used to regulate the higher frequency input signal and enu- merate the frequency,and AT89C51 MicrocontroUer is used to intelligently control and display opration, varied functions are designed:varied time gate,frequency measurement,period measurement,self-calibra- tion,external counter,etc. |
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| Keywords: | Cymometer ECL level High speed chip CPLD Single chip processor |
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