| An Asynchronous 32×8-Bit Multiplier Based on LDCVSPG Logic |
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| 作者姓名： | ZHONG Xiongguang RONG Mengtian School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai China |
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| 作者单位： | ZHONG Xiongguang，RONG Mengtian School of Electronic，Information and Electrical Engineering，Shanghai Jiao Tong University，Shanghai 200030，China |
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| 基金项目： | Supported by the National High Technology Research and Development Program of China (2001AA141040) |
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| 摘 要： | An asynchronous high-speed pipelined 32×8-bit array multiplier based on latched differential cascode voltage switch with pass-gate (LDCVSPG) logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation (CSMC's) 0.6 μm CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.
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