| 高速数字存储示波器的超前滞后电路设计 |
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| 引用本文： | 袁继敏,李小玲,陈长龄.高速数字存储示波器的超前滞后电路设计[J].重庆师范大学学报(自然科学版),2003,20(4):31-33. |
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| 作者姓名： | 袁继敏 李小玲 陈长龄 |
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| 作者单位： | 1. 攀枝花学院,电气信息工程系,四川,攀枝花,617000
2. 电子科技大学,自动化工程学院,成都,610054 |
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| 摘 要： | 数字存储示波器的核心是时基电路，超前／滞后控制电路是时基电路的核心。其设计是数字存储示波器的关键。用可编程语言FPGA实现设计了用前置计数器和后置计数器控制触发点前后的采集样点数和数据的方案。
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| 关 键 词： | 高速数字存储示波器 电路设计 超前控制 滞后控制 计数器 CPLD |
| 文章编号： | 1672-6693(2003)04-0031-03 |
| 修稿时间： | 2002年12月12日 |
A Design to Realize the Lead and Lag Control in Digitizing Oscilloscope |
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| YUAN Ji-min,LI Xiao-ling,CHEN Chang-ling.A Design to Realize the Lead and Lag Control in Digitizing Oscilloscope[J].Journal of Chongqing Normal University:Natural Science Edition,2003,20(4):31-33. |
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| Authors: | YUAN Ji-min LI Xiao-ling CHEN Chang-ling |
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| Institution: | YUAN Ji-min~1,LI Xiao-ling~1,CHEN Chang-ling~2 |
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| Abstract: | The core of digitizing storage oscilloscope is the time-based circuit,while the lead and lag control circuit is the core of the time-based circuit,the design of which is the crux of the digitizing storage oscilloscope.This paper gives a design with the programming language FPGA to realize the control of the samples before and after the trigger point and data storage by the software MUXPLUS. |
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| Keywords: | digitizing storage oscilloscope the lead and lag control counter CPLD simulation |
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