| 直接序列扩频信号快速捕获 |
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| 引用本文： | 李菊,陈禾,吴嗣亮,何佩琨.直接序列扩频信号快速捕获[J].北京理工大学学报,2005,25(10):905-908. |
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| 作者姓名： | 李菊 陈禾 吴嗣亮 何佩琨 |
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| 作者单位： | 北京理工大学,信息科学技术学院电子工程系,北京,100081 |
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| 摘 要： | 提出一种新的基于频域并行搜捕法的改进型快捕电路结构.该结构利用设计复用技术实现FFT单元和IFFT单元的复用;通过软件计算本地伪码FFT,并将其结果存储在ROM中,使硬件规模大幅减少;采用并行设计提高系统的运算速度;采用块浮点算法提高动态范围和运算精度.整个快捕电路由一块FPGA XC2V3000-5实现,工作时钟为29 ns,精度为1/4码片情况下,伪码捕获仅需4.145 ms.仿真和测试结果验证了设计的正确性.
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| 关 键 词： | 直接序列扩频信号 快速捕获 频域并行搜捕法 现场可编程门阵列 直接序列扩频信号 快速捕获 Signals Direct Sequence Acquisition 并行设计 结果验证 测试 仿真 伪码捕获 情况 码片 运算精度 工作时钟 FPGA 路由 高动态范围 块浮点算法 运算速度 系统 |
| 文章编号： | 1001-0645(2005)10-0905-04 |
| 收稿时间： | 11 17 2004 12:00AM |
| 修稿时间： | 2004年11月17日 |
Rapid Acquisition for Direct Sequence Spread-Spectrum Signals |
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| LI Ju,CHEN He,WU Si-liang and HE Pei-kun.Rapid Acquisition for Direct Sequence Spread-Spectrum Signals[J].Journal of Beijing Institute of Technology(Natural Science Edition),2005,25(10):905-908. |
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| Authors: | LI Ju CHEN He WU Si-liang and HE Pei-kun |
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| Institution: | Department of Electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China |
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| Abstract: | A new improved architecture to realize rapid acquisition for direct sequence spread-spectrum signals was presented.To reduce hardware resources,this architecture utilized duplicate design to realize FFT and IFFT in the same unit and calculated the FFT of local code by software and stored it in ROM;this design applied parallel pipeline structure to improve the processing speed;block floating-point arithmetic was used to enhance the dynamic range and computation accuracy.The whole design was implemented with only one chip of XC2V3000-5 FPGA.When working clock was 29 ns and acquisition precision was 1/4 code,the acquisition time would be within 4.145 ms.The validity of design is verified by simulation and measurement results. |
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| Keywords: | direct sequence spread-spectrum signals rapid acquisition frequency domain parallel acquisition method field programmable gate array |
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