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用于单片集成真空传感器的SAR型ADC设计
引用本文:李金凤,唐祯安,汪家奇.用于单片集成真空传感器的SAR型ADC设计[J].大连理工大学学报,2009,49(6):958-963.
作者姓名:李金凤  唐祯安  汪家奇
作者单位:1. 大连理工大学,电子与信息工程学院,辽宁,大连,116024;沈阳化工学院,信息工程学院,辽宁,沈阳,110142
2. 大连理工大学,电子与信息工程学院,辽宁,大连,116024
基金项目:国家自然科学基金资助项目(90607003)
摘    要:设计了一款适用于单芯片集成真空传感器的10位SAR型A/D转换器.轨至轨比较器通过并联两个互补的子比较器实现.信号采样时,比较器进行失调消除,提高电路的转换精度.电路采用0.5μm2P3M标准CMOS工艺制作.系统时钟频率为20MHz,输入电压范围为0~3V.在1.25MS/s采样率和4.6kHz信号输入频率下,电路的信噪比为56.4dB,无杂散动态范围为69.2dB.芯片面积为2mm2.3V电源电压供电时,功耗为3.1mW.其性能已达到高线性度和低功耗的设计要求.

关 键 词:逐次逼近  A/D转换器  低功耗  CMOS  单片集成真空传感器  

Successive approximation register ADC for monolithic vacuum sensor
LI Jinfeng,TANG Zhenan,WANG Jiaqi.Successive approximation register ADC for monolithic vacuum sensor[J].Journal of Dalian University of Technology,2009,49(6):958-963.
Authors:LI Jinfeng  TANG Zhenan  WANG Jiaqi
Institution:LI Jin-feng1,2,TANG Zhen-an1,WANG Jia-qi11.School of Electronic , Information Engineering,Dalian University of Technology,Dalian 116024,China,2.School of Information Engineering,Shenyang University of Chemical Technology,Shenyang 110142
Abstract:A 10-bit successive approximation register analog-to-digital converter (ADC) is presented for monolithic vacuum sensor. Rail to rail comparator is achieved by paralleling two complementary comparators. Offset cancellation circuit is included to improve the precision of the ADC. The circuit is fabricated in a 0. 5 μm 2P3M standard CMOS process. The system clock frequency is 20 MHz and the input voltage changes from 0 to 3 V. The effective chip area is 2 mm~2. The signal to noise and distortion ratio of 56. 4 dB and the spurious-free dynamic range of 69. 2 dB are achieved with 4. 6 kHz sinusoid wave and 1. 25 MS/s sample rate. The power dissipation is 3. 1 mW at 3 V supply voltage. The proposed ADC meets the requirements of high linearity and low power dissipation.
Keywords:successive approximation  analog-to-digital converter(ADC)  low power dissipation  CMOS  monolithic vacuum sensor  
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