一种基于RAM的QC-LDPC码新颖编码架构研究

为了提高LDPC编码器的数据吞吐率,提出了一种基于RAM的改进型准循环LDPC码(quasi-cyclic low density parity-cheek,QC-LDPC)的编码器实现方法.采用RAM存储校验位,并引入指针来指示RAM的地址方法.从而取代传统编码架构中的移位寄存器,使编码过程通过对RAM的读写操作实现,校验位序列也通过对RAM的读操作串行输出.由于该编码器没有使用移位寄存器以及并串转换电路,从而大幅度节约了硬件资源并提高了数据吞吐率.

A novel encoding architecture of QC-LDPC codes based on RAM

In this paper, a method to mend the encoding architecture based on RAM is presented for improved structure quasi-cyclic low density parity check ( QC-LDPC) codes. In this advanced architecture of QC-LDPC codes encoder, the RAM is advisably used to store the parity-check bits and the pointers are introduced as the addresses of the RAM instead of shift registers used for storing the generator of Hqr. Thus, the encoding process can be achieved by reading and writing on RAM and the parity-check bits can be output serially. Because the encoding architecture doesn' t need any shift registers and parallel to serial circuit, hardware resource is saved and the data throughput is improving.