| 基于DSP或FPGA的脉冲压缩实现方法 |
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| 引用本文： | 王德勇,陈祝明,高如鹏.基于DSP或FPGA的脉冲压缩实现方法[J].实验科学与技术,2006,4(4):110-112,116. |
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| 作者姓名： | 王德勇 陈祝明 高如鹏 |
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| 作者单位： | 电子科技大学成都,610054 |
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| 摘 要： | 针对雷达信号脉冲压缩出现的大运算量到底需要多少硬件资源问题，详细地给出了两种频域脉压算法的具体实现步骤及其全程脉压运算量的计算公式；并进行了单芯片FPGA实现高阶脉压算法的仿真。
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| 关 键 词： | 脉冲压缩 重叠相加法 重叠保存法 数字信号处理器 可编程逻辑器件 |
| 文章编号： | 1672-4550（2006）04-0110-04 |
| 收稿时间： | 2006-04-17 |
| 修稿时间： | 2006年4月17日 |
Ways to Realization Pulse Compression Based on DSP or FPGA |
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| WANG De-yong,CHEN Zhu-ming,GAO Ru-peng.Ways to Realization Pulse Compression Based on DSP or FPGA[J].Experiment Science & Technology,2006,4(4):110-112,116. |
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| Authors: | WANG De-yong CHEN Zhu-ming GAO Ru-peng |
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| Institution: | University of Electronic Science and Technology of China Chengdu 610054 |
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| Abstract: | In order to solve the complicated arithmetic for the pulse compression, this paper gives two methods in frequency - domain and one way in time - domain realization. It also gives the equations for arithmetic quantity of each method. Using only one IC to realize pulse compression system has been simulated. |
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| Keywords: | pulse compression overlap addition overlap store DSP FPGA |
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