| 高性能信号处理系统体系结构的研究与实现 |
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| 引用本文： | 何宾,韩月秋.高性能信号处理系统体系结构的研究与实现[J].北京理工大学学报,2003,23(6):759-762. |
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| 作者姓名： | 何宾 韩月秋 |
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| 作者单位： | 北京理工大学,信息科学技术学院电子工程系,北京,100081 |
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| 摘 要： | 构建高性能的并行分布式信号处理系统．在所构建的信号处理系统结构中，摒弃了传统上基于共享总线的互连方法，将RapidIO互连协议应用于基于开关互连的、点对点的多处理器系统体系结构中，并使用可编程门阵列FPGA实现基于RapidIO的DSP节点的通信处理器，对该处理器的性能进行了讨论和分析。
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| 关 键 词： | 信号处理系统 计算机体系结构 可编程门阵列（FPGA） 总线协议 |
| 文章编号： | 1001-0645(2003)06-0759-04 |
| 收稿时间： | 2002/10/9 0:00:00 |
| 修稿时间： | 2002年10月9日 |
Study and Realization of High Performance Signal Processing System |
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| HE Bin and HAN Yue-qiu.Study and Realization of High Performance Signal Processing System[J].Journal of Beijing Institute of Technology(Natural Science Edition),2003,23(6):759-762. |
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| Authors: | HE Bin and HAN Yue-qiu |
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| Institution: | Department of Electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing100081, China;Department of Electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing100081, China |
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| Abstract: | Building up a distributed processing system of high performance is a complex problem and the communication among many processor elements affects the performance of the overall processing system. In the proposed architecture of processing system, the traditional method of bus sharing is avoided and the RapidIO protocol is used to achieve the multi-processor system based on the peer-to-peer and switch; the communication processor to connect DSP is achieved by FPGA (field programmable gate array). Performance of the processor is discussed and analyzed in detail. |
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| Keywords: | signal processing system computer architecture FPGA bus protocol |
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