红豆杉组织、细胞培养物紫杉醇快速检测

利用薄层层析，高效液相色谱，酶联免疫吸附等方法对国内4种1变种红豆杉及其组织，细胞培养物进行紫杉醇快速定性，定量检测，试验结果表明，国内4种1变种红豆杉及其组织，细胞培养物中都含有紫杉醇，其中东北红豆杉及其培养物中紫杉醇含量较高。     

Simultaneous Multithreading Fau Tolerance Processor

Transient fault detection mechanism is added to simultaneous muhithreading architecture. By exploiting both ILP (Instruction l~evel Parallelism) and TLP (Thread Level Parallelism), Simultaneous Multithreading(SMT) Fault Tolerance Processor can be expected to achieve better tradeoff between performance and hardware cost than traditional Fault Tolerance Processors. Detailed simulations of 3 of SPEC95 benchmarks show that executing two redundant programs on the fault-tolerant microarchitecture takes only 40%-61% longer than running a single version of the program. The new instruction fetch algorithm enhances the performance by 0. 4%～1% to most of the benchmarks we choose randomly.     

关于张力腿平台若干术语的定名问题

根据国内外有关文献资料，探讨张力腿平台若干术语的定名问题，给出这些术语的译名和释义。     

In-place structural strength and fatigue analysis for floating platform topsides

This paper presents some insights on the state-of-the-art practice that has been utilized recently in the inplace structural strength and fatigue analysis for topsides on deepwater floating platforms such as tension leg plat-form (TLP) and semi-submersibles. Emphases are put on analysis software,geometric and mass modeling,hydro-dynamic loading and its mapping,and analysis procedures. In addition,for the in-place analysis using structure analysis computer system (SACS),the procedure of Visual Basic for Application (VBA) is developed to map AQWA-LINE hydrodynamic loading to the SACS integrated hull/topsides model;for the in-place analysis using structure engineering system analysis model (SESAM),many computer aided applications are made to aid the post-processing. These applications have been used in structural analyses for a few TLP and semi-submersible plat-form topsides,and are briefly introduced in this paper.     

An AP SoC for a unified architecture

An instruction level parallel computing paradigm and a unified architecture for an array processor (AP) on a chip (SoC) are presented in this paper. Here “APU SoC” is short for “an AP SoC for the unified architecture”. The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing. As a result, all the computing can be implemented on an APU SoC. The APU SoC offers the rationale of an array structure for development in current technology, yet simplicity for the hardware (chip) and software (program) parallel designs. Just as a single processor chip can replace many function module chips, the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing.     

Production TTR modeling and dynamic buckling analysis

In a typical tension leg platform (TLP) design,the top tension factor (TTF),measuring the top tension of a top tensioned riser (TTR) relative to its submerged weight in water,is one of the most important design parameters that has to be specified properly. While a very small TTF may lead to excessive vortex induced vibration (VIV),clashing issues and possible compression close to seafloor,an unnecessarily high TTF may translate into excessive riser cost and vessel payload,and even has impacts on the TLP sizing and design in general. In the process of a production TTR design,it is found that its outer casing can be subjected to compression in a worst-case scenario with some extreme metocean and hardware conditions. The present paper shows how finite element analysis (FEA) models using beam elements and two different software packages (Flexcom and ABAQUS) are constructed to simulate the TTR properly,and especially the pipe-in-pipe effects. An ABAQUS model with hybrid elements (beam elements globally + shell elements locally) can be used to investigate how the outer casing behaves under compression. It is shown for the specified TTR design,even with its outer casing being under some local compression in the worst-case scenario,dynamic buckling would not occur;therefore the TTR design is adequate.     

一种基于TLP输入的系统级ESD模型分析方法

基于已有的传输线脉冲发生器(TLP)与IEC 61000-4-2应力的等效关系, 提出一种以TLP应力作为输入的系统级模型分析方法。与传统的IEC应力作为系统输入的分析方法相比, 该方法解决了对流入待测器件(DUT)残余能量的计算不够精确的问题, 同时提高了DUT失效预测方面的精准性。通过SPICE仿真, 预测了上述两种应力作为系统输入的DUT失效情况。通过相应的印制电路板(PCB)的实测验证, 进一步说明新提出的方法能够提高系统级失效预测的精准性。     

海洋油气开采张力腿平台的水动力性能

 基于三维势流理论,在API风谱及JONSWAP波浪谱环境条件下,通过计算分析,研究了海洋油气开采张力腿平台的水动力性能。结果表明,张力腿平台的水平面外运动受到的波浪载荷,随着波浪频率的增大呈现快速下降趋势;垂荡、横摇及纵摇运动响应在波浪频率为0.4 rad/s时达到峰值,且垂荡运动位移不超过工作水深的5%,摇角不超过5°,体现了张力腿平台半刚性的运动特点;二阶差频波浪载荷作用于张力腿平台的y方向力约为x方向力的4倍,与一阶波浪载荷相比,二阶差频波浪载荷相对较小,但对张力腿平台的水平面内运动影响不容忽视。     

TLP hull structural design and analysis

Tension leg platform (TLP) has been one of the most favorite deep-water platform concepts for offshore oil and gas field exploration and development. As of now,a total of 24 TLPs have been installed worldwide with 3 more to be installed in the near future and 5 more under design. Most of these installations are in the Gulf of Mexico (GoM). Water depths for these TLP installations range from 150 m to 1 600 m. It is highly expected that China will have her first TLP designed,fabricated,and installed in the very near future. In order to satisfy the need for a unified hull structural design practice,this paper presents the design philosophy of a conventional TLP hull structure with emphases on critical structural components design and analysis methodologies.     

一种片上低触发电压高耐压NMOS ESD防护结构设计

设计了一种触发电压低于10 V,HBM耐压超过4kV的低触发、高耐压NMOS ESD防护结构.通过带钳位的栅耦合RC网络来适当抬升ESD泄放管栅压与衬底电压.在提高泄放能力与降低触发电压的同时,依然保持了较高的二次击穿电流It,从而增强了MOS防护结构在深亚微米CMOS电路中的ESD防护能力.该结构最终在CSMC HJ018工艺流片,并通过TLP测试平台测得触发电压低于10V,二次击穿电流3.5A,达到设计要求.