基于FPGA的信号量管理模块的设计

针对软件实时操作系统的开销给嵌入式系统带来性能退化的问题,提出了基于FPGA的硬件实时操作系统的方案,设计了一个硬件信号量管理模块并用Verilog HDL硬件描述语言进行描述。仿真结果验证了这一设计的正确性,且其创建、请求和发送信号量操作的执行速度比μC/OS-Ⅱ中信号量管理部分明显提高。     

一种高效纯化血清淀粉样物质A(SAA)的方法

通过密度梯度超速离心、脱脂从急性相胸水中分离得到含有血清淀粉样物质A（Serum AmyloidA,SAA）的高密度脂蛋白（HDL），再通过两次Sephacry1S-200层析纯化SAA蛋白。经SDS-PAGE电泳和Western Blotting检验证实得到的SAA蛋白纯度高，可作为抗原免疫动物制备抗体，方法可用于从胸水中大量制备SAA。     

基于Verilog HDL的卡尔曼滤波器的仿真研究

文章对卡尔曼滤波器的算法的5个递推方程进行了详细的介绍,并采用Verilog HDL硬件描述语言对卡尔曼滤波器的算法进行了仿真研究.通过仿真分析,结果表明卡尔曼滤波器的系统过程噪声、测量噪声、系统阶数(递归次数)等因素对滤波结果有影响。     

Apolipoprotein M affecting lipid metabolism or just catching a ride with lipoproteins in the circulation?

Apolipoprotein M (apoM) is a novel apolipoprotein found mainly in high-density lipoproteins (HDL). Its function is yet to be defined. ApoM (25 kDa) has a typical lipocalin ?-barrel fold and a hydrophobic pocket. Retinoids bind apoM but with low affinity and may not be the natural ligands. ApoM retains its signal peptide, which serves as a hydrophobic anchor to the lipoproteins. This prevents apoM from being lost in the urine. Approximately 5% of HDL carries an apoM molecule. ApoM in plasma (1 μM) correlates strongly with both low-density lipoprotein (LDL) and HDL cholesterol, suggesting a link to cholesterol metabolism. However, in casecontrol studies, apoM levels in patients with coronary heart disease (CHD) and controls were similar, suggesting apoM levels not to affect the risk for CHD in humans. Experiments in transgenic mice suggested apoM to have antiatherogenic properties; possible mechanisms include increased formation of pre-? HDL, enhanced cholesterol mobilization from foam cells, and increased antioxidant properties. Received 28 November 2008; received after revision 15 December 2008; accepted 16 December 2008     

PLI-CRC校验码在EoS封装技术中的实现

EoS( Ethernet over SDH)技术结合了SDH和以太网两者的优势,实现了以太网数据在SDH上传输.针对硬件资源优化及EoS系统中数据帧长PLI的CRC-16校验码算法特点,提出基于FPGA的改进实现方法,通过电路仿真与综合结果表明,该方法实现了对高速并行化数据传输的有效保护,在资源消耗、实现效率两方面都取得了较好效果.     

基于EDA工具的数字电子系统设计

介绍了基于 EDA工具的硬件电子系统的设计方法 ,并针对特定的在系统可编程 CPL D器件 isp L SI10 16目标芯片描述了自动洗衣机模拟控制器的程序设计步骤 ,给出了 HDL程序代码     

基于FPGA的VGA图像控制器的设计与实现

VGA（视频图形阵列）是一种标准的显示接口，伴随着嵌入式系统的迅速发展，尤其是高速图像处理的发展．埘可以将实时图像处理进行显示有了更多的需求．这里依据VGA接口原理采用了Verilog HDL语言对Altera的Cyclone系列FPGA（现场可编程门阵列）进行了设计，并验证了结果。通过采用FPGA设计VGA接口可以将要显示的数据直接送到显示器，节省了计算机的处理过程，加快了数据的处理速度，节约了硬件成本。     

最优状态编码研究

探讨了状态机电路最优状态编码的问题。研究了状态编码的成本及寄存器最优、组合逻辑最优之间的关系，介绍了3种常用的编码方法。通过实验分析差异。     

基于VerilogHDL的流水线的设计方法及应用

采用流水线式方法设计通讯系统，可提高系统的工作速度。通过实例给出了流水线式设计方法的应用方法，验证了该方法是可行的。     

Molecular pathogenesis of apolipoprotein E-mediated amyloidosis in late-onset Alzheimer’s disease

Apolipoprotein E (apoE) ɛ4 allele is a genetic risk factor for late-onset familial and sporadic Alzheimer’s disease (AD). In the central nervous system, apoE is secreted mainly by astrocytes as a constituent of high-density lipoproteins. A recent study using apoE knockout mice provided strong evidence that apoE promotes cerebral deposition of amyloid β protein (Aβ). However, no clear explanation of the pathogenesis of apoE-induced AD has been provided. Here we discuss two possible mechanisms by which apoE might enhance Aβ deposition. One is the intracellular pathway in which apoE is internalized by neurons and induces lysosomal accumulation of Aβ and amyloidogenic APP (amyloid precursor protein) fragments, leading to neuronal death. The other is the extracellular pathway in which apoE-containing lipoproteins are trapped by Aβ1–42 deposits mobilizing soluble Aβ peptides and consequently enlarge amyloid plaques. These two mechanisms may operate at different stages of AD pathogenesis and suggest a chaperone-like function for the apoE molecule. Received 4 February 1999; received after revision 9 April 1999; accepted 23 April 1999