后摩尔时代的基于一维纳米材料的CMOS技术

基于碳纳米管的场效应晶体管技术源于1998年,在随后的近10年间p型（空穴型）场效应晶体管的制备技术日趋完善,其性能全面超过相对应的硅基场效应晶体管．最近北京大学研究组关于高性能室温弹道n型（电子型）碳纳米管场效应晶体管的研究为基于碳纳米管的CMOS（complementary metal—oxide—semiconductor）技术的腾飞装上了另一个翅膀．特别是这种技术无需掺杂,加上碳纳米管特殊的几何和电子结构使得基于碳纳米管的CMOS技术有望突破传统微电子工艺所面临的一些根本性的困难,为下一步实现基于碳纳米管的纳电子电路的规模集成奠定了基础．     

碳纳米管场效应晶体管:现状和未来

硅基互补型金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)场效应晶体管工艺已经发展到了14 nm技术节点,预计将很快到达其极限,需要寻找新的信息器件来延续摩尔定律.由于具备超小尺寸、高迁移率等显著优点,碳纳米管被认为是后摩尔时代最有潜力替代硅作为晶体管沟道的纳米材料之一.经过近20年的研究,基于碳纳米管场效应晶体管的技术已经取得了巨大的进步.本文将回顾碳纳米管场效应晶体管领域的关键性技术,包括N型欧姆接触实现、"无掺杂"CMOS技术、自对准顶栅结构以及尺寸缩减技术等.而且我们将分析碳纳米管晶体管在大规模材料制备以及碳管和电极接触方面存在的问题,并提出可能的解决方案.在此基础上,通过分析实验数据和模拟结果,对碳纳米管电子学的未来发展做出预测和展望,结果表明碳纳米管晶体管的潜力巨大,通过对材料和器件结构进行合理优化,碳纳米管晶体管在性能上可能远远超过硅基半导体对应技术节点的晶体管,成为后摩尔时代极其具有竞争力的信息器件.     

单电子晶体管/场效应管混合存储单元数值分析

基于背景电荷不敏感单电子晶体管/场效应晶体管混合存储单元利用单电子晶体管源漏电流随栅电压周期振荡的特性工作,以半经典的单电子正统理论为基础,采用计算机数值模拟的方法,分析了背景电荷不敏感单电子晶体管/常规场效应晶体管混合存储单元的工作原理和基本特性.提出了存储单元中分别以三结电容耦合单电子晶体管和单电子旋转栅替代双结单电子晶体管的新结构,其主要思想是通过增加单电子器件中的串联隧道结数来抑制各种噪声.模拟结果表明,新结构的系统性能,特别是抗噪声性能有一定提高     

电解液栅型碳纳米管场效应晶体管的实验研究

由于碳纳米管具有独特的结构和性能,因而一直受到人们的关注.对于包括碳纳米管场效应管在内的分子元件的研究方面尤其令人注目.笔者研究了具有电解液栅的碳纳米管场效应晶体管,研究中所用的碳纳米管是用热灯丝化学气相沉积法(CVD)合成的.衬底材料是平面玻璃,Fe/Ni混合物用作催化剂.对具有Ag电极的多壁碳纳米管晶体管作了优化设计制造,并利用KCl溶液作为栅极.实验结果表明,电解液栅型碳纳米管晶体管(FET)呈现出良好的电流-电压特性曲线.在栅压2 V时,其跨导约为0.5 mA/V.并对获得的研究结果进行了讨论.     

硅双栅MOS场效应晶体管的模型和实验特性

硅双栅MOS场效应晶体管或称MOS场效应四级管(简写为DG—MOSFET′S),是一种超高频、低噪声、增益可控的新型固体电子器件。本文是根据电流连续性原理系统的推证了该器件的物理模型及实验特性。其结果通过电子计算机所计算出的工作曲线与实测都基本与Brown和Barsan等人的一致。故本文认为这是一种比单栅MOS场效应晶体管(简写为SG—MOSFET′S)性能好,应用更加广泛的MOSFET器件。     

单电子晶体管/场效应管混合存储单元数值分析

基于背景电荷不敏感单电子晶体管／场效应晶体管混合存储单元利用单电子晶体管源漏电流随栅电压周期振荡的牲工作,以半经典的单电子正统理论为基础,采用计算机数值模拟的方法,分析了背景电荷不敏感单电子晶体管／常规场效应晶体管混合存储单元的工作原理和基本特性,提出了存储单元中分别以三结电容耦合单电子晶体管和电子旋转栅替代双结单电子晶体管的新结构,其主要思想是通过增加单电子器件中的串联随道结数来抑制各种噪声。模     

基于碳纳米管的CMOS逻辑电路的模拟和优化

基于查表模型,利用SPICE(simulation program with integrated ciruit emphasis)电路模拟软件,首次模拟了互补型碳纳米管(CNT)场效应晶体管组成的反相器,模拟结果和实验结果吻合,实现了碳纳米管场效应晶体管的实际测量数据和半经验查表模型的衔接.利用直流特性分析和瞬态特性分析等仿真手段研究了CNT CMOS反相器的功耗和门延迟特性随工作电压和器件阈值电压变化的关系,并对电路设计和工作状态提出了优化方案.进一步模拟了与非门和或非门,并提出了电路的优化方案.     

BD_101型半导体表面钝化台

本文主要是介绍BD-101型半导体表面钝化台.评述了用化学汽相淀积方法生长二氧化硅膜使硅表面钝化的工作.该项工作导致集成电路用的双极晶体管和绝缘栅场效应晶体管的性能和稳定性得到提高.     

场效应晶体管在低电平下变阻特性的数学模型

本文介绍了场效应晶体管在低电平下变阻特性的物理概念及其用途; 并叙述了如何通过实验,测出实验数据,然后根据数据处理原理并借助于计算机求出其数学模型。     

处理放大器的同步分离电路

本文介绍了一种高性能的电视同步分离电路;计算了自动增益控制闭环迴路方程;提出了作为压控电阻用于反馈迴路的场效应晶体管的选择原则.最后给出了典型场效应晶体管3DO_1F及3DJ6E的实测压控电阻特性.     

Bandgap modulation of carbon nanotubes by encapsulated metallofullerenes

Motivated by the technical and economic difficulties in further miniaturizing silicon-based transistors with the present fabrication technologies, there is a strong effort to develop alternative electronic devices, based, for example, on single molecules. Recently, carbon nanotubes have been successfully used for nanometre-sized devices such as diodes, transistors, and random access memory cells. Such nanotube devices are usually very long compared to silicon-based transistors. Here we report a method for dividing a semiconductor nanotube into multiple quantum dots with lengths of about 10nm by inserting Gd@C82 endohedral fullerenes. The spatial modulation of the nanotube electronic bandgap is observed with a low-temperature scanning tunnelling microscope. We find that a bandgap of approximately 0.5eV is narrowed down to approximately 0.1eV at sites where endohedral metallofullerenes are inserted. This change in bandgap can be explained by local elastic strain and charge transfer at metallofullerene sites. This technique for fabricating an array of quantum dots could be used for nano-electronics and nano-optoelectronics.     

面向SWCNT-FET制造的介电泳装配技术

针对单壁碳纳米管(SWCNT)场效应晶体管(FET)制造过程中面临的SWCNT装配问题,采用介电泳技术实现SWCNT在微电极上的有效装配.对SWCNT在非均匀电场中所受到的介电泳力进行了相关理论分析,利用COMSOL多物理场耦合软件模拟了介电泳驱动电场,并做了大量装配实验,获得了高效装配SWCNT所需的实验参数.AFM扫描观测及电特性测试验证了这种方法的有效性,同时也为其他一维纳米材料纳电子器件的装配制造提供了借鉴.     

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Semiconducting carbon nanotubes and nanowires are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs) owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes and Ge/Si core/shell nanowires. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-kappa dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures and enhanced gate coupling with high-kappa dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS microm(-1)) and on-current (2.1 mA microm(-1)) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, tau = CV/I, which represents a key metric for device applications, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.     

Indium phosphide nanowires as building blocks for nanoscale electronic and optoelectronic devices

Nanowires and nanotubes carry charge and excitons efficiently, and are therefore potentially ideal building blocks for nanoscale electronics and optoelectronics. Carbon nanotubes have already been exploited in devices such as field-effect and single-electron transistors, but the practical utility of nanotube components for building electronic circuits is limited, as it is not yet possible to selectively grow semiconducting or metallic nanotubes. Here we report the assembly of functional nanoscale devices from indium phosphide nanowires, the electrical properties of which are controlled by selective doping. Gate-voltage-dependent transport measurements demonstrate that the nanowires can be predictably synthesized as either n- or p-type. These doped nanowires function as nanoscale field-effect transistors, and can be assembled into crossed-wire p-n junctions that exhibit rectifying behaviour. Significantly, the p-n junctions emit light strongly and are perhaps the smallest light-emitting diodes that have yet been made. Finally, we show that electric-field-directed assembly can be used to create highly integrated device arrays from nanowire building blocks.     

Ballistic carbon nanotube field-effect transistors

A common feature of the single-walled carbon-nanotube field-effect transistors fabricated to date has been the presence of a Schottky barrier at the nanotube--metal junctions. These energy barriers severely limit transistor conductance in the 'ON' state, and reduce the current delivery capability--a key determinant of device performance. Here we show that contacting semiconducting single-walled nanotubes by palladium, a noble metal with high work function and good wetting interactions with nanotubes, greatly reduces or eliminates the barriers for transport through the valence band of nanotubes. In situ modification of the electrode work function by hydrogen is carried out to shed light on the nature of the contacts. With Pd contacts, the 'ON' states of semiconducting nanotubes can behave like ohmically contacted ballistic metallic tubes, exhibiting room-temperature conductance near the ballistic transport limit of 4e(2)/h (refs 4-6), high current-carrying capability (approximately 25 micro A per tube), and Fabry-Perot interferences at low temperatures. Under high voltage operation, the current saturation appears to be set by backscattering of the charge carriers by optical phonons. High-performance ballistic nanotube field-effect transistors with zero or slightly negative Schottky barriers are thus realized.     

单电子晶体管(SET)及其应用

当电子器件的尺寸接近纳米尺度时，量子效应对器件工作的影响变得格外重要，就需要采用具有新机理的晶体管结构，单电子晶体管（SET）就是其中一个典型的结构，文中对比传统晶体管（MOSFET）的工作原理，分析了单电子晶体管SET的工作机理，简要概述了SET的一些应用。     

一种深亚微米CMOS工艺驱动电感式互联缓冲器工作模式的研究

研究了互补金属-氧化物半导体(CMOS)的栅极驱动电阻-电感-电容(RLC)互联的实际工作模式。采用α-指数模型,对深亚微米CMOS线驱动器晶体管工作区内的片上互联电感效应进行了分析。这项研究表明在缓冲区切换时,线性和饱和的工作模式有可能同时存在,因而饱和区和线性区模型都不能单独用来表征晶体管的工作模式。还提出了一种工作在饱和区的线驱动器的MOS管开关时间部分的计算效率的闭合表达式。相比较具有较宽范围行参数的SPICE仿真来说,提出的公式具有15%的准确性,特别适合CAD工具的实施。     

低电压并五苯薄膜场效应晶体管

利用全蒸镀法, 以并五苯作为有源层, 聚甲基丙烯酸甲 酯（PMMA）作为绝缘层, 制备了全有机薄膜场效应晶体管（TFT）. 测试结果表明, 器件具有较低的工作电压和较高的场效应迁移率. 对工作机理进行了探讨.     

Low-voltage organic transistors with an amorphous molecular gate dielectric

Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick gate dielectric layers: these dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in dielectric thickness leads to ever greater gate leakage and power dissipation.