| 基于SystemVerilog的SoC功能验证方法研究 |
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| 引用本文： | 程刚,蔡敏.基于SystemVerilog的SoC功能验证方法研究[J].科学技术与工程,2009,9(22). |
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| 作者姓名： | 程刚 蔡敏 |
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| 作者单位： | 华南理工大学电子与信息学院,广州,510641 |
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| 摘 要： | SoC功能复杂度不断提高,结合了最新验证语言SystemVerilog的断言、随机约束、功能覆盖率等特点以及Verification Methodology Manual(VMM)验证架构,对SoC验证的各阶段进行了改进.模块验证阶段灵活应用了形式验证和动态仿真验证;集成验证阶段依据可重性的思想搭建验证环境、采用迭代开发的思想提前了集成验证启动时间;系统验证阶段采取了软硬件协同验证;同时利用随机约束技术开发验证向量,利用功能覆盖率技术评价随机约束向量对功能的覆盖.通过这些改进措施达到了提SoC功能验证效率的目的.
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| 关 键 词： | 单元验证 集成验证 系统验证 |
| 收稿时间： | 2009/7/21 0:00:00 |
| 修稿时间： | 2009/7/27 0:00:00 |
Research of SoC Functional Verification Based on SystemVerilog |
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| Cheng Gang and Cai Min.Research of SoC Functional Verification Based on SystemVerilog[J].Science Technology and Engineering,2009,9(22). |
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| Authors: | Cheng Gang and Cai Min |
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| Institution: | School of Electronic and Information Engineering, South China University of Technology |
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| Abstract: | This paper basing on VMM and SystemVerilog which is a new verification language, introduces how to improve the efficiency of functional verification by modifying unit verification, integrated verification and system verification in SoC design process. |
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| Keywords: | SystemVerilog |
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