| 二维DCT算法的高速芯片设计 |
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| 引用本文： | 钟文荣,陈建发. 二维DCT算法的高速芯片设计[J]. 厦门大学学报(自然科学版), 2005, 44(2): 198-201 |
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| 作者姓名： | 钟文荣 陈建发 |
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| 作者单位： | 厦门大学电子工程系,福建,厦门,361005 |
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| 摘 要： | 介绍了一种基于行列变换快速算法的高速DCT处理芯片的设计，并详细阐述了实现这一算法的电路结构．为了提高芯片的处理速度，电路中采用了流水线结构和双RAM转置存储技术，并给出FPGA实现和Verilog综合结果．综合结果显示，该芯片最高可以工作在140MHz的时钟频率上，非常适合于各种视频图像压缩方面的实时应用．
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| 关 键 词： | DCT FPGA 芯片 设计方案 视频压缩技术 二维DCT算法 编码 |
| 文章编号： | 0438-0479(2005)02-0198-04 |
| 修稿时间： | 2004-03-16 |
FPGA Implementation of High Throughput 2D-DCT |
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| ZHONG Wen-rong,CHEN Jian-fa. FPGA Implementation of High Throughput 2D-DCT[J]. Journal of Xiamen University(Natural Science), 2005, 44(2): 198-201 |
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| Authors: | ZHONG Wen-rong CHEN Jian-fa |
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| Abstract: | The discrete cosine transform(DCT) has been widely used in the implementation of low bit rate codes for video compression as an integral part of several international standards.In this paper,we present a high throughput 2D-DCT architecture with circuit designs in details,based on the algorithm of matrix row-column transposition.In order to improve the throughput performance,two technologies of pipeline structure and Double RAM Buffer are employed.At the end of this paper,the FPGA implementation and Verilog synthesis results are provided,which shows that the clock rate can achieve up to 140 MHz.It is well suited for the application in real time image and video compression system. |
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| Keywords: | DCT FPGA VLSI design video compression |
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