| 一种串行高速芯片互连接口逻辑设计与实现 |
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| 引用本文： | 李仁刚.一种串行高速芯片互连接口逻辑设计与实现[J].科学技术与工程,2012,12(31):8235-8240. |
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| 作者姓名： | 李仁刚 |
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| 作者单位： | 1. 高效能服务器和存储技术国家重点实验室,济南250013;浪潮(北京)电子信息产业有限公司,北京100085
2. 浪潮(北京)电子信息产业有限公司,北京,100085 |
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| 基金项目： | 国家重点基础研究发展计划（973计划）;国家科技攻关计划 |
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| 摘 要： | 在计算机系统中,总线技术对整个系统的性能和功能都有直接影响,通过研究高速信号传输的特点,分析串行高速芯片互连协议,实现了一种串行高速芯片互连接口逻辑,并实现了FPGA平台的与处理器互连和芯片间互连的验证。最终达到了设计性能要求和可靠性要求,互连接口数据传输速率达到6.4GT/s。
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| 关 键 词： | 串行总线接口 扰码 FPGA 可靠性 |
| 收稿时间： | 2012/6/25 0:00:00 |
| 修稿时间： | 7/16/2012 1:27:06 PM |
Design and Implementation of a Serial High-Speed Chip Interconnect Interface Logic |
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| lirengang.Design and Implementation of a Serial High-Speed Chip Interconnect Interface Logic[J].Science Technology and Engineering,2012,12(31):8235-8240. |
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| Authors: | lirengang |
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| Institution: | 2(State Key Laboratory of High-end Server & Storage Technology1,Jinan 250013,P.R.China; Inspur(Beijing) Electronic Information Industry Co.,Ltd.2,Beijing 100085,P.R.China) |
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| Abstract: | Bus technology has a direct impact on the performance and functionality of computer system. By study the characteristics of high-speed signal transmission, analysis the specification of serial high-speed chip interconnection, the paper implement a logic of serial high-speed chip interconnect interface, and verification with FPGA platform in processor interconnect and chip interconnect. Eventually meet the requirements of the performance and reliability, the data transfer rates of interface is 6.4GT/s. |
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| Keywords: | Serial Bus Interface Scramble FPGA Reliability |
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