| TGS 中的一种逻辑电路模型及预处理 |
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| 引用本文： | 欧阳星明. TGS 中的一种逻辑电路模型及预处理[J]. 华中科技大学学报(自然科学版), 1997, 0(8) |
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| 作者姓名： | 欧阳星明 |
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| 作者单位： | 华中理工大学计算机科学与工程系 |
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| 摘 要： | 讨论了逻辑电路测试生成系统（简称ＴＧＳ）中使用的一种模型数据及预处理方法．用简单的表格描述了电路的网络结构，给出了测试生成所需要的数据．并通过对数据进行预处理，加速了测试生成过程，提高了整个系统的效率
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| 关 键 词： | 逻辑电路；测试生成；模型数据；数据生成；故障精简 |
A Logic Circuit Model and the Preprocessing for TGS |
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| Ouyang Xingming, Dept. of Computer Sci. , Eng.,HUST,Wuhan ,China.. A Logic Circuit Model and the Preprocessing for TGS[J]. JOURNAL OF HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY.NATURE SCIENCE, 1997, 0(8) |
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| Authors: | Ouyang Xingming Dept. of Computer Sci. & Eng. HUST Wuhan China. |
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| Affiliation: | Ouyang Xingming, Dept. of Computer Sci. & Eng.,HUST,Wuhan 430074,China. |
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| Abstract: | A kind of model data and the preprocessing method for the logic circuit test generation system (TGS) are presented. The network structure of the circuit is described using simple tables and the data needed for the test generation is given. The process of test generation is quickened and the system efficiency is improved with the preprocessing of data. |
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| Keywords: | logic circuit test generation model data data generation fault reduction |
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