| 一层半模式的宏单元阵列版图自动设计及验证系统MALS |
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| 引用本文： | 洪先龙,于泓涛,周强,王尔乾,宋建宁,陈允康. 一层半模式的宏单元阵列版图自动设计及验证系统MALS[J]. 清华大学学报(自然科学版), 1988, 0(4) |
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| 作者姓名： | 洪先龙 于泓涛 周强 王尔乾 宋建宁 陈允康 |
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| 作者单位： | 计算机科学与技术系 (洪先龙，于泓涛，王尔乾)，计算机科学与技术系(周强)，电机工程系(宋建宁)，电机工程系(陈允康) |
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| 摘 要： | 本文提出的 ＭＡＬＳ系统，针对一层半模式门阵的特点，以线网均匀分配为主要目标 的布局和总体布线算法以及分区、定序、预测和并行横向的通道布线算法，提高了布图 的成功率。系统还提供了多种方式可进行人工干预的交互环境及布图正确性验证手段。 已用ＭＡＬＳ设计了若干芯片，表明该系统是有效的。
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| 关 键 词： | 超大规模集成电路 计算机辅助设计布图 宏单元阵列 |
An Automatic Design and Verification System for One-and-a-half Layer Macro-Cell Gate Array (MALS) |
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| Hong Xianlong,Yu Hongtao,Zhou Qiang,Wang Erqian. An Automatic Design and Verification System for One-and-a-half Layer Macro-Cell Gate Array (MALS)[J]. Journal of Tsinghua University(Science and Technology), 1988, 0(4) |
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| Authors: | Hong Xianlong Yu Hongtao Zhou Qiang Wang Erqian |
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| Abstract: | The gate array with Si-gate CMOS technology and one-and-a-half layer routing are widely used in IC design fabrication, because of its advantages in simple technical support and saving of the chip area. However. it usually uses pre-fixed channel width and limited routing tracks for crossing the macro-cell columns. These limitations give automatic design system many troublesome problems. Therefore many existing algorithms for placemen and routing can not be applied. To accommodate the characteristics of onet -and-a-half layer macrocell gate array. MALS uses new placement and global and channel routing algorithms. The MALS also provides many interactive environment, extraction and verification utilities for the designer to improve the layout and confirming the correctness of their mask layout. The MALS has been used to the design of several chips and is proved as an effective design tool. |
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| Keywords: | VLSI CAD layout macro-cell gate array |
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