故障攻击硬件仿真中低成本电路状态控制方法

为了解决基于FPGA的故障注入攻击仿真中,由于使用全扫描方法处理待测电路造成的逻辑资源消耗大的问题,提出一种用部分扫描电路实现电路状态完全可控的方法,即在任何时刻都可以改变电路中所有触发器的值,模拟故障注入攻击,进而在设计阶段对集成电路的安全性进行早期评估。将电路抽象为图,扩展平衡结构部分扫描测试方法,通过扫描触发器选择和触发器使能添加实现对所有触发器的同时控制。采用SAT可满足性算法,基于电路逻辑产生故障测试矢量集,实现故障注入仿真。结果表明,相较于全扫描电路,部分扫描方法以新增少量输入端口为代价,平均减少28.04%的扫描触发器,进而降低故障注入攻击硬件仿真的逻辑资源消耗。

Low-cost state control method for hardware emulation of fault attack

In order to reduce the logic overhead caused by the full scan method in the FPGA-based fault injection attack emulation, this study proposes a partial scan based method for the simultaneous control of circuit states, i. e. , setting the values of all flip-flops in the circuit at any time, to emulate the fault injection attack. This emulation allows the early security assessment of integrated circuits during the design phase. Meanwhile, the method abstracts the circuit as a graph, extends the balanced-structure based partial scan method to select flip-flops, and then adds enable signals to achieve simultaneous control of all flip-flops. In addition, based on circuit logic, the SAT satisfiability algorithm is used to generate fault test vectors to be injected. The experimental results show that compared with the full scan, the proposed method reduces the number of scanning flip-flops by 28. 04% on average, which reduces the logic overhead in the hardware emulation of fault injection attack at the cost of adding a small number of input ports.